General Description
The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits.

FEATUREs
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge, and auto refresh modes
• Self refresh mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply