GENERAL DESCRIPTION
The GLT44032-E 4Mbit Embedded DRAM (EmDRAM) is  an asynchronous design with non-multiplexed row and  column addressing scheme.   RAS, CAS, WE and OE control the memory operations.
Byte Write operation is controlled by DQM[0], DQM[1],  DQM[2], and DQM[3]. DQM[0] going LOW will mask  DI[0:7] from writing into memory; DQM[1] going LOW  will mask DI[8:15] from writing into memory; DQM[2]  going LOW will mask DI[16:23] from writing into memory; DQM[3] going LOW will mask DI[24:31] from writing  into memory. All output drivers, DO[0:31], will be Threestated during a Write operation.

FEATURES
◆ Logical organization: 128Kx32 bits
◆ Physical organization: 512x256x32
◆ Single 3.3v ± 0.3v power supply
◆ 512-cycle refresh in 8 ms
◆ Refresh modes: RAS only, CBR, and Hidden
◆ Single CAS with 4 DQM for Byte Write control
◆ Non-multiplex row and column addresses
◆ Separate I/O operation
◆ 80/100 MHz page mode EDO cycle