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GLT44032-E-35

128K x 32 Embedded EDO DRAM Macro

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GLT44032-E

128K x 32 Embedded EDO DRAM Macro

FEATURES

x Logical organization: 128Kx32 bits

x Physical organization: 512x256x32

x Single 3.3v ± 0.3v power supply

x 512-cycle refresh in 8 ms

x Refresh modes: RAS only, CBR, and Hidden

x Single CAS with 4 DQM for Byte Write control

x Non-multiplex row and column addresses

x Separate I/O operation

x 80/100 MHz page mode EDO cycle

GENERAL DESCRIPTION

The GLT44032-E 4Mbit Embedded DRAM (EmDRAM) is

an asynchronous design with non-multiplexed row and

column addressing scheme. RAS, CAS, WE and OE

control the memory operations.

Byte Write operation is controlled by DQM[0], DQM[1],

DQM[2], and DQM[3]. DQM[0] going LOW will mask

DI[0:7] from writing into memory; DQM[1] going LOW

will mask DI[8:15] from writing into memory; DQM[2]

going LOW will mask DI[16:23] from writing into mem-

ory; DQM[3] going LOW will mask DI[24:31] from writing

into memory. All output drivers, DO[0:31], will be Three-

stated during a Write operation.

Performance Data

Parameter

Max. RAS access time, tRAC

Max. RAS precharge time, tRP

Max. column address access time, tAA

Max. CAS access time, tCAC

Min. extended data out page mode cycle time, tPC

Min. read/write cycle time, tRC

-30

30 ns

20 ns

12 ns

8 ns

10 ns

60 ns

-35

35 ns

25 ns

14 ns

10 ns

12.5 ns

70 ns

May 1997 (Rev. 1) 1

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