Functional Description
The CY7C1335 is a 3.3V, 32K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

FEATUREs
• Supports 100-MHz bus for Pentium® and PowerPC™ operations with zero wait states
• Fully registered inputs and outputs for pipelined operation
• 32K by 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
    — 4.2 ns (for 133-MHz device)
    — 5.5 ns (for 100-MHz device)
    — 7.0 ns (for 75-MHz device
• User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option