CY7C1335-100AC(1999) Просмотр технического описания (PDF) - Cypress Semiconductor
Номер в каталоге
Компоненты Описание
Список матч
CY7C1335-100AC Datasheet PDF : 15 Pages
| |||
aven’t
re
CY7C1335
32K x 32 Synchronous-Pipelined Cache RAM
2CY 7 C13 29
Features
• Supports 100-MHz bus for Pentium and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 32K by 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 4.2 ns (for 133-MHz device)
— 5.5 ns (for 100-MHz device)
— 7.0 ns (for 75-MHz device
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1335 is a 3.3V, 32K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A[14:0]
15
GW
BWE
BW 3
BW2
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
CLR
Q1
Q
ADDRESS
CE
D
REGISTER
13
D DQ[31:24] Q
BYTEWRITE
REGISTERS
D DQ[23:16] Q
BYTEWRITE
REGISTERS
BW1
BW0
CE1
CE2
CE3
D DQ[15:8] Q
BYTEWRITE
REGISTERS
D DQ[7:0] Q
BYTEWRITE
REGISTERS
D
CE
ENABLE
REGISTER
Q
CLK
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 4.2 ns (133-MHz
device).
The CY7C1335 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
13
15
32KX32
MEMORY
ARRAY
32
32
D
Q
ENABLE DELAY
REGISTER
CLK
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[31:0]
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 30, 1999
Share Link: 