General Description
The 21143 is an Ethernet LAN controller for both 100-Mb/s and 10-Mb/s data rates, which provides a direct interface to the peripheral component interconnect (PCI) local bus or the CardBus. The 21143 interfaces to the host processor by using onchip command and status registers (CSRs) and a shared host memory area, set up mainly during initialization. This minimizes processor involvement in the 21143 operation during normal reception and transmission.
The 21143 is optimized for low power PCI/CardBus based systems and supports two types of power-management mechanisms. The main mechanism is based upon the OnNow architecture, which is required for PC 97 and PC 98. The alternative mechanism is based upon the older remote wake-up-LAN mechanism.

Product Features
■ Fully compliant with Revision 2.1 of the PCI Local Bus Specification and with Revision 1.0 of the PCI Bus Power Management Interface Specification.
■ Fully compliant with Revision 1.0 of the Advanced Configuration and Power Interface (ACPI) Specification and with Revision 1.0 of the Network Device Class Power Management Specification, under the OnNow Architecture for Microsoft’s PC 97 Hardware Design Guide and PC 98 System Design Guide.
■ Supports IEEE 802.3 with full Auto-Negotiation algorithm of full-duplex and half-duplex operation for 10 Mb/s and 100 Mb/s (NWAY).
■ Supports IEEE 802.3 and ANSI 8802-3 Ethernet standards.
■ Supports direct memory access (DMA) and has direct interface to both the CardBus* and PCI local bus.
■ Provides glueless 32-bit PCI bus master interface.
■ Contains large independent receive and transmit FIFOs.
■ Contains internal PCS and scrambler/descrambler for MII/SYM interface for 100BASE-TX.
■ Contains onchip integrated AUI port and a 10BASE-T transceiver.
■ Supports autodetection between 10BASE-T, AUI, and MII/SYM ports.
■ Provides an upgradable boot ROM interface up to 256KB.
■ Supports remote wake-up-LAN and Magic Packet* with the SecureON™ password option.
■ Supports PCI/CardBus clock speed frequency from dc to 33 MHz; network operation with PCI clock from 20 MHz to 33 MHz.
■ Implements low-power management with two power-saving modes (sleep and snooze).
■ Implements low-power, 3.3-V CMOS technology.