21143 Просмотр технического описания (PDF) - Intel

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21143

PCI/CardBus 10/100 Ethernet LAN Controller

Intel 

21143

Contents

1.0 21143 OVERVIEW .......................................................................................................................... 1

1.1 General Description ............................................................................................................ 2

1.2 Microarchitecture ................................................................................................................ 3

2.0 PINOUT ........................................................................................................................................... 5

2.1 Signal Reference Tables .................................................................................................... 7

2.2 Signal Reference Tables .................................................................................................... 9

2.3 Pin Tables.........................................................................................................................15

2.4 Signal Grouping by Function ............................................................................................17

3.0 ELECTRICAL AND ENVIRONMENTAL SPECIFICATIONS........................................................19

3.1 Voltage Limit Ratings........................................................................................................19

3.2 Temperature Limit Ratings ...............................................................................................19

3.3 Power Specifications ........................................................................................................ 20

3.4 PCI Bus and CardBus Electrical Parameters ...................................................................20

3.4.1 PCI and CardBus I/O Voltage Specifications ...................................................21

3.4.2 System Bus Reset ............................................................................................22

3.4.3 PCI and CardBus Clock Specifications ............................................................22

3.4.4 Other PCI and CardBus Signals.......................................................................24

3.5 AUI and Twisted-Pair DC Specifications ..........................................................................25

3.6 Serial Interface Attachment Specifications .......................................................................26

3.6.1 Serial Clock Timing ..........................................................................................26

3.6.2 Internal SIA Mode AUI Timing—Transmit ........................................................27

3.6.3 Internal SIA Mode AUI Timing—Receive .........................................................28

3.6.4 Internal SIA Mode AUI Timing—Collision.........................................................28

3.6.5 Internal SIA Mode 10BASE-T Interface Timing—Transmit ..............................29

3.6.6 Internal SIA Mode 10BASE-T Interface Timing—Receive ...............................30

3.6.7 Internal SIA Mode 10BASE-T Interface Timing—Idle Link Pulse .....................31

3.7 MII Interface Specifications ..............................................................................................32

3.8 MII/SYM Port Timing ........................................................................................................32

3.8.1 MII/SYM 10/100-Mb/s and 10-Mb/s Timing—Transmit ....................................32

3.8.2 MII/SYM 10/100-Mb/s Timing—Receive ..........................................................34

3.8.3 SYM 10/100-Mb/s Timing—Signal Detect ........................................................35

3.8.4 MII 10/100-Mb/s Timing—Receive Error ..........................................................35

3.8.5 MII 10/100-Mb/s Timing—Carrier Sense and Collision ....................................36

3.9 Boot ROM and Serial ROM Port Specification .................................................................36

3.10 Boot ROM Port Timing .....................................................................................................37

3.10.1 Boot ROM Read Timing ...................................................................................37

3.10.2 Boot ROM Write Timing....................................................................................38

3.11 Serial ROM Port Timing....................................................................................................39

3.12 External Register Timing ..................................................................................................39

3.13 Joint Test Action Group—Test Access Port .....................................................................41

3.13.1 JTAG DC Specifications ...................................................................................41

3.13.2 JTAG Boundary-Scan Timing...........................................................................42

4.0 MECHANICAL SPECIFICATIONS ...............................................................................................43

Preliminary Datasheet

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