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MAS3507D

MPEG 1/2 Layer 2/3 Audio Decoder

Micronas 

PRELIMINARY DATA SHEET

MAS 3507D

2. Functional Description of the MAS 3507D

2.1. DSP Core

The hardware of the MAS 3507D consists of a high

performance RISC Digital Signal Processor (DSP) and

appropriate interfaces (see Fig. 2–1). The internal pro-

cessor works with a memory word length of 20 bits

and an extended range of 32 bits in its accumulators.

The instruction set of the DSP is highly optimized for

audio data compression and decompression. Thus,

only very small areas of internal RAM and ROM are

required. All data input and output actions are based

on a ‘non cycle stealing’ background DMA that does

not cause any computational overhead.

2.2. Firmware (Internal Program ROM)

A valid MPEG 1/2/2.5 layer 2/3 data signal is taken as

input. The signal lines are a clock line SIC and the data

line SID. The MPEG decoder performs the audio

decoding. The steps for decoding are

– synchronization,

– side information extraction,

– audio data decoding,

– ancillary data extraction, and

– volume and tone control.

For the supported bit rates and sample rates, see

Table 3–12 on page 32. Frame synchronization and

CRC-error signals are provided at the output pins of

the MAS 3507D in serial input mode.

MPEG Bit Stream

Sync

Digital Audio Output

Volume

Tone

Control

MPEG

Decoder

Ancillary

Data

Decoder

Status

Config. Reg.

PIO

Status

Start-up Config.

Fig. 2–1: Block diagram of the MPEG Decoder in serial input mode

to µC

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