MAS3507D Просмотр технического описания (PDF) - Micronas

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MAS3507D

MPEG 1/2 Layer 2/3 Audio Decoder

Micronas 

PRELIMINARY DATA SHEET

MAS 3507D

2.7. Interfaces

The MAS 3507D uses an I2C control interface,

2 selectable serial input interfaces for MPEG bit

stream (SDI, SDI*) , a parallel I/O interface (PIO) for

MPEG- or ADPCM-data and a digital audio output

interface (SDO) for the decoded audio data (I2S or

similar). Additionally, the parallel I/O interface (PIO)

may be used for monitoring and mode selection tasks.

The PIO lines are defined by the internal firmware.

2.7.1. MPEG Bit Stream Interface (SDI)

The MPEG bit stream input interface uses the three

pins: SIC, SII, and SID. For MPEG decoding operation,

the SII pin must always be connected to VSS.

The serial interface has to be initialized before the

first use. Otherwise no output signal is produced.

After Power-up or a rising slope on Pin PORQ, write

the following I2C-command, while SIC is hold low:

W $3A 68 93 B0 00 02

(write $0020 into register $3B)

W $3A 68 00 01

(execute “RUN 1” command)

The MPEG input signal format is shown in Fig. 2–4.

The data values are latched with the falling edge of the

SIC signal.

The MPEG bit stream generated by an encoder is

unformatted. It will be formatted (e.g. 8 bit or 16 bit) by

storing on a media (Flash-RAM, Harddisk). The serial

data required from the MPEG bit stream interface must

be in the same bit order as produced by the encoder.

2.7.2. SDI* Selection

An alternative serial input (SDI*) is available. The alter-

native serial input can be selected by setting register

SI1M0 at address $4f (see Table 2–3).

Table 2–3: SDI* Selection via Register SI1M0,

$4f (write)

Value

0

2

Function

use SDI lines

use PI14...PI16 pins for

serial input (named SDI*)

Vh

SIC

Vl

Vh

SII

Vl

data valid

latch data at falling edge of clock

Vh

SID

Vl

Fig. 2–4: Schematic timing of the SDI (MPEG) input

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