PE9721 Просмотр технического описания (PDF) - Peregrine Semiconductor Corp.
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PE9721 Datasheet PDF : 13 Pages
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PE9721
Preliminary Specification
Enhancement Register
The Enhancement Register is a buffered serial shift
register, loaded from the Serial Data Port. It
activates special test and operating modes in the
PLL. The bit assignments for these modes are
shown in Table 11.
The functions of these Enhancement Register bits
are shown in Table 12. A function becomes active
when its corresponding bit is set HIGH. Note that
bits 1, 2, 5, and 6 direct various data to the Dout
pin, and for valid operation no more than one
should be set HIGH simultaneously.
The Enhancement Register is buffered to prevent
inadvertent control changes during serial loading.
Data that has been loaded into the register is
captured in the buffer and made available to the
PLL on the falling edge of E_WR.
A separate control line is provided to enable and
disable the Enhancement mode. Functions are
enabled by taking the ENH control line LOW.
Table 11. Enhancement Register Bit Assignments
Reserved
EE Register
Output
fp output
B0
B1
B2
Power
down
B3
Counter
load
B4
MSEL
output
B5
fc output Reserved
B6
B7
Table 12. Enhancement Register Functions
Bit Function
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Reserved
EE Register Output
fp output
Power down
Counter load
MSEL output
fc output
Reserved
Program to 0
Allows the contents of the EE Register to be serially shifted out Dout, LSB (B0) first.
Data is shifted on rising edge of Clock.
Provides the M counter output at Dout.
Powers down all functions except programming interface.
Immediate and continuous load of counter programming.
Provides the internal dual modulus prescaler modulus select (MSEL) at Dout.
Provides the R counter output at Dout.
Program to 0
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Copyright Peregrine Semiconductor Corp. 2003
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