PE9721 Просмотр технического описания (PDF) - Peregrine Semiconductor Corp.
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PE9721 Datasheet PDF : 13 Pages
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PE9721
Preliminary Specification
Lock Detect Output
A lock detect signal is provided at pin LD, via the pin
CEXT (see Figure 1). CEXT is the logical “NAND” of
PD_U and PD_D waveforms, driven through a series
2k ohm resistor. When the loop is locked, this output
will be HIGH with narrow pulses LOW. Connecting
CEXT to an external shunt capacitor provides
integration of this signal.
The CEXT signal is sent to the LD pin through an
internal inverting comparator with an open drain
output. Thus LD is an “AND” function of PD_U and
PD_D.
Table 7. Serial Interface
S_WR E_WR EELoad Register Loaded
0
0
0
1
0
X
0
Primary Register
0
Enhancement Register
1
EE Register
Serial Data Port
The Serial Data Port allows control data to be
entered into the device. This data can be directed
into one of three registers: the Enhancement
register, the Primary register, and the EE register.
Table 7 defines the control line settings required to
select one of these destinations.
Input data presented on pin 5 (Data) is clocked
serially into the designated register on the rising
edge of Clock. Data is always loaded LSB (B0) first
into the receiving register. Figure 3 defines the
timing requirements for this process.
Figure 3. Serial Interface Timing Diagram
Data
E_WR
EELoad
tEC
tCE
Clock
S_WR
tDSU
tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
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Copyright Peregrine Semiconductor Corp. 2003
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