PE9721 Просмотр технического описания (PDF) - Peregrine Semiconductor Corp.
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PE9721 Datasheet PDF : 13 Pages
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Figure 2. Pin Configuration
VDD 1
GND 2
ENH 3
S_WR 4
Data 5
Clock 6
GND 7
FSel 8
E_WR 9
VPP 10
VDD 11
Fin 12
24 fr
23 GND
22 EESel
21 N/C
20 CP
19 VDD
18 Dout
17 LD
16 EELoad
15 Cext
14 GND
13 Fin
PE9721
Preliminary Specification
Table 1. Pin Descriptions
Pin No. Pin Name Type
1
VDD
(Note 1)
2
GND
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Ground.
3
ENH
Input
Enhancement mode control line. When asserted LOW, enhancement register bits are functional. Internal
70kΩ pull-up resistor.
4
S_WR
Input
Secondary Register WRITE input. Primary Register contents are copied to the Secondary Register on S_WR
rising edge. Also used to control Serial Port operation and EEPROM programming.
5
Data
Input
Binary serial data input. Input data entered LSB (B0) first.
6
Clock
Input
Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit EE Register, or the 8-bit
Enhancement Register on the rising edge of Clock. Also used to clock EE Register data out Dout port.
7
GND
Ground.
8
FSel
Input
Frequency Register selection control line. Internal 70kΩ pull-down resistor.
9
E_WR
Input
Enhancement Register write enable. Also functions as a Serial Port control line. Internal 70kΩ pull-down
resistor.
10
VPP
Input
EEPROM erase/write programming voltage supply pin.
11
VDD
(Note 1) Same as pin 1.
12
Fin
Input
Prescaler input from the VCO.
13
Fin
Input
Prescaler complementary input. A series 50 Ω resistor and DC blocking capacitor should be placed as close as
possible to this pin and connected to the ground plane.
14
GND
Ground.
15
CEXT
Output
Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2kΩ series resistor. Connecting CEXT to an
external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
16
EELoad
Control line for Serial Data Port, Frequency Register selection, EE Register parallel loading, and EEPROM
programming. Internal 70kΩ pull-down resistor.
17
LD
Output,
OD
Lock detect output, an open-drain logical inversion of CEXT. When the loop is in lock, LD is high impedance;
otherwise, LD is a logic LOW.
18
Dout
Output
Data out function. Dout is defined with the Enhancement Register and enabled with ENH.
19
VDD
(Note 1) Same as pin 1.
20
CP
Output
Charge pump output. Sources current is when fc leads fp and sinks current when fc lags fp.
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0098~01B | UTSi CMOS RFIC SOLUTIONS
Page 2 of 13
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