HD6433024F Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HD6433024F

Hitachi Single-Chip Microcomputer

Hitachi -> Renesas Electronics 

5.1.2 Block Diagram ...................................................................................................... 82

5.1.3 Pin Configuration .................................................................................................. 83

5.1.4 Register Configuration .......................................................................................... 83

5.2 Register Descriptions.......................................................................................................... 83

5.2.1 System Control Register (SYSCR) ....................................................................... 83

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB).............................................. 84

5.2.3 IRQ Status Register (ISR) ..................................................................................... 89

5.2.4 IRQ Enable Register (IER) ................................................................................... 90

5.2.5 IRQ Sense Control Register (ISCR)...................................................................... 91

5.3 Interrupt Sources ................................................................................................................ 92

5.3.1 External Interrupts................................................................................................. 92

5.3.2 Internal Interrupts.................................................................................................. 93

5.3.3 Interrupt Exception Handling Vector Table.......................................................... 93

5.4 Interrupt Operation ............................................................................................................. 97

5.4.1 Interrupt Handling Process.................................................................................... 97

5.4.2 Interrupt Exception Handling Sequence ............................................................... 102

5.4.3 Interrupt Response Time ....................................................................................... 103

5.5 Usage Notes........................................................................................................................ 104

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction....................... 104

5.5.2 Instructions that Inhibit Interrupts......................................................................... 105

5.5.3 Interrupts during EEPMOV Instruction Execution ............................................... 105

Section 6 Bus Controller .................................................................................................. 107

6.1 Overview ............................................................................................................................ 107

6.1.1 Features ................................................................................................................. 107

6.1.2 Block Diagram ...................................................................................................... 108

6.1.3 Pin Configuration .................................................................................................. 109

6.1.4 Register Configuration .......................................................................................... 110

6.2 Register Descriptions.......................................................................................................... 110

6.2.1 Bus Width Control Register (ABWCR)................................................................ 110

6.2.2 Access State Control Register (ASTCR) .............................................................. 111

6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 112

6.2.4 Bus Release Control Register (BRCR) ................................................................. 116

6.2.5 Bus Control Register (BCR) ................................................................................. 117

6.2.6 Chip Select Control Register (CSCR)................................................................... 119

6.2.7 Address Control Register (ADRCR)..................................................................... 120

6.3 Operation ............................................................................................................................ 121

6.3.1 Area Division ........................................................................................................ 121

6.3.2 Bus Specifications ................................................................................................. 124

6.3.3 Memory Interfaces ................................................................................................ 125

6.3.4 Chip Select Signals................................................................................................ 125

6.3.5 Address Output Method ........................................................................................ 126

6.4 Basic Bus Interface............................................................................................................. 127

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