ISL6521 Просмотр технического описания (PDF) - Renesas Electronics
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ISL6521 Datasheet PDF : 14 Pages
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ISL6521
OSC
VOSC
VIN
DRIVER1
PWM
COMP
+-
ZFB
SYNC
DRIVER
LO
PHASE
VOUT
CO +
ESR
(PARASITIC)
VE/A
+
ERROR
AMP
ZIN
0.8V
DETAILED COMPENSATION COMPONENTS
C2
C1 R2
ZFB
VOUT
ZIN
C3 R3
COMP
RS1
FB
-
+
RP1
ISL6521
0.8V
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
FLC=
-------------------1--------------------
2 LO CO
FESR= -2-------------E----S--1---R----------C-----O---
The compensation network consists of the error amplifier
(internal to the ISL6521) and the impedance networks ZIN and
ZFB. The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f0dB and 180
degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC)
3. Place 2ND Zero at Filter’s Double Pole
4. Place 1ST Pole at the ESR Zero
5. Place 2ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FN9148 Rev 2.00
Feb 8, 2005
Compensation Break Frequency Equations
FZ1 = 2--------------R---1--2---------C-----1--
FZ2 = 2----------------R-----S----1---1-+-----R-----3------------C-----3--
FP1
=
---------------------------1---------------------------
2
R2
C-C----11-----+-----CC-----22--
FP2 = 2--------------R---1--3---------C-----3--
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 5. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at FP2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 6 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
FZ1
FZ2 FP1 FP2
OPEN LOOP
ERROR AMP GAIN
80
20
log
V--V---P-I--N-P---
60
40
COMPENSATION
GAIN
20
0
-20
20log -R-R----S--2--1--
MODULATOR
-40
GAIN
FLC FESR
-60
10
100
1K
10K 100K
FREQUENCY (Hz)
CLOSED LOOP
GAIN
1M 10M
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Individual Output Disable
The PWM and linear controllers can independently be
shutdown.
To disable the switching regulator, use an open-drain or open-
collector device capable of pulling the OCSET pin (with the
attached ROCSET pull-up) below 1.25V. To minimize the
possibility of OC trips at levels different than predicted, a
COCSET capacitor with a value of an order of magnitude larger
than the output capacitance of the pull-down device, has to be
Page 8 of 14
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