FM25V01A Просмотр технического описания (PDF) - Cypress Semiconductor

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FM25V01A

128-Kbit (16K × 8) Serial (SPI) F-RAM

Cypress Semiconductor 

FM25V01A

Power Cycle Timing

Over the Operating Range

Parameter

Description

Min

tPU

Power-up VDD(min) to first access (CS LOW)

1

tPD

Last access (CS HIGH) to power-down (VDD(min))

0

tVR [11, 12]

VDD power-up ramp rate

50

tVF [11, 12]

VDD power-down ramp rate

100

tREC [13]

Recovery time from sleep mode

–

Figure 18. Power Cycle Timing

VDD

VDD(min)

tVR

tPU

VDD(min)

tVF

tPD

CS

Max Unit

–

ms

–

µs

–

µs/V

–

µs/V

400

µs

Notes

11. Slope measured at any point on VDD waveform.

12. These parameters are guaranteed by design and are not tested.

13. Refer to Figure 14 for sleep mode recovery timing.

Document Number: 001-90881 Rev. *E

Page 17 of 22

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