MD56V62160E-10 Просмотр технического описания (PDF) - LAPIS Semiconductor Co., Ltd.

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MD56V62160E-10

4-Bank x 1,048,576-Word x 16-Bit SYNCHRONOUS DYNAMIC RAM

LAPIS Semiconductor Co., Ltd. 

FEDD56V62160E-07

MD56V62160E

Bank Interleave Page Read Cycle @CAS Latency = 2, Burst Length = 4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLK

CKE

CS

Note 1

High

RAS

CAS

ADDR RAa

CAa

RBb

CBb

A12,

A13

A10

RAa

RBb

CAc

CBd

CAe

DQ

QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

IROH

WE

UDQM,

LDQM

Row Active

(A-Bank)

Row Active

(B-Bank)

Read Command

(A-Bank)

Read Command

(B-Bank)

Read Command

(B-Bank)

Precharge Command

(A-Bank)

Read Command

(A-Bank)

Read Command

(A-Bank)

*Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle.

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