MD56V62160E-10 Просмотр технического описания (PDF) - LAPIS Semiconductor Co., Ltd.

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MD56V62160E-10

4-Bank x 1,048,576-Word x 16-Bit SYNCHRONOUS DYNAMIC RAM

LAPIS Semiconductor Co., Ltd. 

FEDD56V62160E-07

MD56V62160E

Page Read & Write Cycle (Same Bank) @CAS Latency  2, Burst Length = 4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLK

CKE

High

CS

RAS

Bank A Active

CAS

ADDR

A12,

A13

A10

ICCD

Ca0

Cb0

Cc0

Cd0

DQ

Qa0 Qa1 Qb0 Qb1

Dc0 Dc1 Dd0

lOWD

tWR Note 2

WE

UDQM,

LDQM

Note 1

Read Command

Read Command

Write Command

Precharge Command

Write Command

*Notes: 1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the

write command to avoid bus contention.

2. To assert row precharge before a burst write ends, wait tWR after the last write data input.

Input data during the precharge input cycle will be masked internally.

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