FEDD56V62160E-07
MD56V62160E
Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length = 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
Note 1
Note 1
CKE
CS
RAS
CAS
ADDR Ra
Ca
A12,
A13
A10
Ra
Cb
Cc
DQ
Qa0 Qa1 Qa2
Qb0 Qb1
Dc0
Dc2
tOHZ
Note 2
tOHZ
Note 3
WE
UDQM,
LDQM
Row Active
CLOCK
Suspension
Read Command
Read DQM
Read Command
Read DQM
Write
DQM
Write DQM
Write
CLOCK Suspension
Command
*Note: 1. When Clock Suspension is asserted, the next clock cycle is ignored.
2. When UDQM and LDQM are asserted, the read data after two clock cycles is masked.
3. When UDQM and LDQM are asserted, the write data in the same clock cycle is masked.
4. When LDQM is set High, the input/output data of DQ1 – DQ8 is masked.
5. When UDQM is set High, the input/output data of DQ9 – DQ16 is masked.
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