CY7C1480BV33 Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C1480BV33 Datasheet PDF : 36 Pages
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
DQs inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BWX) are asserted active to conduct a Write to the desired byte.
ADSC-triggered Write accesses require a single clock cycle to
complete. The address presented to A is loaded into the address
register and the address advancement logic when being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation remain unaltered. A synchronous self-timed Write
mechanism is provided to simplify the Write operations.
Because the CY7C1480BV33, CY7C1482BV33, and
CY7C1486BV33 are a common I/O device, the Output Enable
(OE) must be deasserted HIGH before presenting data to the
DQs inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
provide a 2-bit wraparound counter, fed by A1: A0, that
implements either an interleaved or linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
When in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid, and the completion of the operation is not guaranteed. The
device must be deselected before entering the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1: A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00
01
10
11
Second
Address
A1: A0
01
10
11
00
Third
Address
A1: A0
10
11
00
01
Fourth
Address
A1: A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to Sleep current
ZZ Inactive to exit Sleep current
Test Conditions
ZZ > VDD – 0.2 V
ZZ > VDD – 0.2 V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Min
–
–
2tCYC
–
0
Max
120
2tCYC
–
2tCYC
–
Unit
mA
ns
ns
ns
ns
Document Number: 001-15145 Rev. *F
Page 10 of 36
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