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ZR36050 Просмотр технического описания (PDF) - Zoran Corporation

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ZR36050
ZORAN
Zoran Corporation ZORAN
ZR36050 Datasheet PDF : 52 Pages
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ADVANCE INFORMATION
ZR36050
CLK_IN
CBUSY
CCS
CWE
CAEN
CODE
Figure 16. Master Mode Compressed Data Write in Encoding, Shown for Bus Cycle Time of Two CLK_IN
Pixel Interface
The pixel interface operates synchronously in all modes of oper-
ation, transferring an image data sample in or out every CLK_IN,
when enabled to do so. The DSYNC and STOP signals control
the flow of data on the PIXEL bus, DSYNC indicating which clock
cycles contain valid data, and STOP acting as a request to halt
data transfer for an arbitrary time interval. An additional signal,
EOS, indicates the end of a scan. In encoding modes, PIXEL,
DSYNC and EOS are inputs and STOP is an output, whereas in
decoding modes, PIXEL, DSYNC and EOS are outputs and
STOP is an input.
In the JPEG Baseline encoding and decoding modes, image
data is transferred on the PIXEL bus a block at a time, and
DSYNC indicates the beginning of a block. DSYNC is active for
one CLK_IN cycle, preceding the first sample of a block, and is
always followed by a burst of 64 image samples.
In the Fast Preview decoding mode, and in JPEG Lossless
encoding and decoding, where image data is transferred in a line
by line raster, DSYNC is active in the CLK_IN cycle preceding
each sample.
JPEG Baseline Encoding
In JPEG Baseline encoding, the Pixel Interface samples the
most significant eight bits of the PIXEL bus.
Figure 17 shows two consecutive blocks of image samples
being input at the beginning of a scan, or after a break in data
transfer. Note that the figure shows the second block immediate-
ly following the first, however, this is not necessarily the case.
The first sample of the second block could be separated from the
last sample of the first block by any number of clocks, by
delaying the activation of DSYNC.
CLK_IN
DSYNC
PIXEL
0
1
2
62
63
0
1
2
FIRST BLOCK
SECOND BLOCK
Figure 17. Beginning of a Scan in JPEG Baseline Encoding
22

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