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A3G4250D Просмотр технического описания (PDF) - STMicroelectronics

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A3G4250D Datasheet PDF : 44 Pages
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Digital interfaces
A3G4250D
Figure 16. Multiple byte SPI write protocol (2-byte example)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
MS AD5 AD4 AD3 AD2 AD1 AD0
5.2.3
Note:
SPI read in 3-wire mode
3-wire mode is entered by setting the SIM (SPI serial interface mode selection) bit to 1 in
CTRL_REG2.
Figure 17. SPI read protocol in 3-wire mode
CS
SPC
SDI/O
RW
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
MS AD5 AD4 AD3 AD2 AD1 AD0
The SPI read command is performed with 16 clock pulses:
Bit 0: READ bit. The value is 1.
Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple
reading.
Bit 2-7: address AD(5:0). This is the address field of the indexed register.
Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
The multiple read command is also available in 3-wire mode.
If the A3G4250D is used in a multi-SPI slave environment (several devices sharing the
same SPI bus), the accelerometer can be forced by software to remain in SPI mode. This
objective can be achieved by sending, at the beginning of the SPI communication, the
following sequence to the device:
a = read(0x05)
write(0x05, (0x20 OR a))
The programming of this register makes it possible to enhance the robustness of the SPI
system.
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Doc 022768 Rev 3

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