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A3G4250D Datasheet PDF : 44 Pages
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A3G4250D
5
Digital interfaces
Digital interfaces
The registers embedded in the A3G4250D may be accessed through both the I2C and SPI
serial interfaces. The latter may be software-configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the
CS line must be tied high (i.e., connected to Vdd_IO).
Table 11. Serial interface pin description
Pin name
Pin description
CS
SCL/SPC
SDA/SDI/SDO
SPI enable
I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI
communication mode / I2C disabled)
I2C serial clock (SCL)
SPI serial port clock (SPC)
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SDO
SPI serial data output (SDO)
I2C least significant bit of the device address
5.1
I2C serial interface
The A3G4250D I2C is a bus slave. The I2C is employed to write data to registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
Table 12. I2C terminology
Term
Description
Transmitter
Receiver
The device which sends data to the bus
The device which receives data from the bus
Master
Slave
The device which initiates a transfer, generates clock signals and terminates a
transfer
The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bi-directional line used for sending and receiving the data
to/from the interface. Both lines must be connected to Vdd_IO through an external pull-up
resistor. When the bus is free both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with normal
mode.
Doc 022768 Rev 3
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