MAX1460 Просмотр технического описания (PDF) - Maxim Integrated

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MAX1460

Low-Power, 16-Bit Smart ADC

Maxim Integrated 

MAX1460

Low-Power, 16-Bit Smart ADC

0.010

0.008

0.006

0.004

0.002

0

-0.002

0.004

-0.006

-0.008

-0.010

-100 -80 -60 -40 -20 0 20 40 60 80 100

SENSOR SIGNAL INPUT OR ADC INPUT/OUTPUT RANGE (%)

Figure 2a. Analog Front-End INL (typical)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

-100 -80 -60 -40 -20 0 20 40 60 80 100

SENSOR SIGNAL INPUT OR ADC INPUT/OUTPUT RANGE (%)

Figure 2c. Analog Front-End Noise Standard Deviation of the

Samples (typical)

front-end settings when the sensor’s characteristics are

unknown. Use the tabulated values (Tables 1 and 2) if the

peak sensor excursions are known. See the Test System

Interface section for details on writing these analog front-

end bits.

The PGA gain and the CO are very stable, but are not

accurate. Manufacturing variances on the gain and off-

set of the MAX1460 analog front-end superposition the

residual sensor errors, and are later removed during final

calibration.

For example, suppose the sensor’s sensitivity is +10mV/V

with an offset of -12mV/V. Let the supply voltage be

4

3

2

1

0

-1

-2

-3

-4

-100 -80 -60 -40 -20 0 20 40 60 80 100

SENSOR SIGNAL INPUT OR ADC INPUT RANGE (%)

Figure 2b. Analog Front-End Differential Nonlinearity (DNL)

(typical)

+5V. The full scale (-FS) output of the sensor is then

+5V(-12mV/V) = -60mV; +FS is then +5V (-12mV/V +

10mV/V) = -10mV. Following through the flowchart, the

PGA gain setting is +3 (gain = 93V/V) and the CO cor-

rection setting is +1 (+25mV RTI) - (Referred-to Input).

The coarsely corrected -FS input to the ADC is (-60mV +

25mV)93 = -3.255V. The +FS input to the ADC is (-10mV

+ 25mV)93 = +1.395V. The input range of the ADC is

±VDD. Thus the maximum and minimum digitized sen-

sor signals become -3.255 / 5 = -0.651 and +1.395 / 5 =

+0.279.

Notice that the bridge multiplies the signal by VDD and the

ADC divides the signal by VDD. Thus, the system is ratio-

metric and not dependent on the DC value of VDD. The

ADC output clips to ±1.0 when input values exceed ±VDD.

The best signal-to-noise ratio (SNR) is achieved when the

ADC input is within ±85% of VDD (Figure 2).

The MAX1460 includes an internal temperature-sensing

bridge allowing the MAX1460 temperature to be used as

a proxy for the sensor temperature. For this reason the

MAX1460 must be mounted in thermal proximity to the

sensor. The output of the temperature-sensing bridge

is also corrected by a 3-bit coarse-offset DAC and pro-

cessed by the ADC. The selection of the Temperature

Sensor Offset (TSO) bits in the configuration register

should be made so that the digitized temperature signal is

as close to 0.0 as possible at midscale temperature. This

is done to maximize the dynamic range of the thermal-

calibration coefficients (Table 3).

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