MAX1460 Просмотр технического описания (PDF) - Maxim Integrated

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MAX1460

Low-Power, 16-Bit Smart ADC

Maxim Integrated 

MAX1460

Low-Power, 16-Bit Smart ADC

Table 6. Configuration Register Bitmap

EEPROM

ADDRESS

(HEX)

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

BIT

POSITION

DESCRIPTION

0 (LSB)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15 (MSB)

CO-0 (LSB)

CO-1 (MSB)

CO-S (Sign)

PGA-1 (MSB)

PGA-0 (LSB)

Maxim Reserved

Maxim Reserved

Op Amp Power-Down

Maxim Reserved

TSO-0 (LSB)

TSO-1

TSO-2 (MSB)

Maxim Reserved

Maxim Reserved

Maxim Reserved

Repeat Mode

Writing to the Internal EEPROM

The test system writes to the EEPROM with commands

4 hex (Block-Erase the entire EEPROM), 2 hex (Write

“1” to a single EEPROM bit) and 0 hex (NOOP). During

normal operation (when the TEST pin is low) or when

the test system issues instructions A hex or E hex (Start

conversion from EEPROM values), the DSP reads the

Calibration Coefficients from the EEPROM.

In the normal production flow, determine the calibra-

tion coefficients using direct register access. Then load

the calibration coefficients into the EEPROM with tester

instruction 2 hex. Instruction 4 hex block-erases the

EEPROM and is necessary only for a rework or reclaim

operation. For each part, the Maxim reserved bits in the

Configuration Register should be read before instruction

4 hex is issued, and restored afterwards. The MAX1460

is shipped with its internal EEPROM uninitialized, except

for the reserved bits.

The internal 128-bit EEPROM is arranged as eight 16- bit

words. These eight words are the configuration register

and the seven calibration-coefficient values (Table 7).

The MAX1460 EEPROM is bit addressable. The final cali-

bration coefficients must be mapped into the EEPROM

locations that are to be set. There is no bitclear instruc-

tion. Any EEPROM write operation is necessarily long

because the internal charge pump must create and main-

tain voltages above 20V long enough to cause a reliably

permanent change in the memory.

Writing an EEPROM bit requires 6ms, so writing the

EEPROM typically requires less than 400ms. Do not

decrease the EEPROM write times.

To write an EEPROM bit, the test system must be compli-

ant with the Command Timing Diagram shown in Figure

3, performing the following operations:

1) Issue command 0 hex, including the EEPROM address

field of the bit to be written.

2) Issue command 2 hex, with the address field used in

step 1. Continuously repeat this command 375 times

(6ms).

3) Issue command 0 hex, including the EEPROM address

field used in steps 1 and 2.

The procedure for using command 4 hex (Block-Erase

the EEPROM) is similar. Record the Maxim Reserved bits

in the configuration register prior to using this command,

and restore them afterwards. The number of Block-Erase

operations should not exceed 100.

1) Issue command 0 hex.

2) Issue command 4 hex. Continuously repeat this com-

mand 375 times (6ms).

3) Issue command 0 hex.

Test System Interface:

Observing the DSP Operation

Test system commands 8 hex and A hex initiate a conver-

sion while allowing the test system to observe the opera-

tion of the DSP. To calibrate a unit, the test system must

know the digitized temperature and sensor signals, stored

in DSP registers 8 and 9, and the calibrated and compen-

sated output stored in DSP register 10. The test system

should also verify the EEPROM contents, registers 0–7.

All these signals pass through DSP register S during the

execution of the instruction ROM microcode. The SDO pin

outputs the S register values, and the SDIO pin tells the

tester which signal is currently on S.

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