MAX1460 Просмотр технического описания (PDF) - Maxim Integrated

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MAX1460

Low-Power, 16-Bit Smart ADC

Maxim Integrated 

MAX1460

Low-Power, 16-Bit Smart ADC

Pin Description

PIN

NAME

1, 2, 12,

13, 18, 19,

31, 32, 36,

41–45

N.C.

3

AGND

4

START

5

I.C.

6

D6

7

D7

8

D8

9

D9

10

D10

11

D11

14, 37, 38

15

VDD

VSS

16,17

CS1,

CS2

20

SDIO

21

SDO

22

RESET

23

EOC

24

D0

25

D1

26

D2

FUNCTION

No Connection. Not internally connected.

Analog Ground. Connect to VDD and VSS using 10kΩ resistors (see Functional Diagram).

Optional conversion start input signal, used for extending sensor warm-up time. Internally pulled to

VDD with a 1MΩ (typical) resistor.

Internally Connected. Leave unconnected.

Parallel Digital Output - bit 6

Parallel Digital Output - bit 7

Parallel Digital Output - bit 8

Parallel Digital Output - bit 9

Parallel Digital Output - bit 10

Parallel Digital Output - bit 11 (MSB)

Positive Supply Voltage Input. Connect a 0.1μF bypass capacitor from VDD to VSS. Pins 14, 37, and

38 must all be connected to the positive power supply on the PCB.

Negative Supply Input

Chip-Select Input. The MAX1460 is selected when CS1 and CS2 are both high. When either CS1 or

CS2 is low, all digital outputs are high impedance and all digital inputs are ignored. CS1 and CS2 are

internally pulled high to VDD with a 1MΩ (typical) resistor.

Serial Data Input/Output. Used only during programming/testing, when the TEST pin is high. The

test system sends commands to the MAX1460 through SDIO. The MAX1460 returns the current

instruction ROM address and data being executed by the DSP to the test system. SDIO is internally

pulled to VSS with a 1MΩ (typical) resistor. SDIO goes high impedance when either CS1 or CS2 is

low and remains in this state until the test system initiates conversion.

Serial Data Output. Used only during programming/testing. SDO allows the test system to monitor the

DSP registers. The MAX1460 returns to the test system results of the DSP current instruction. SDO is

high impedance when TEST is low.

Reset Input. When TEST is high, a low-to-high transition on RESET enables the MAX1460 to accept

commands from the test system. This input is ignored when TEST is low. Internally pulled high to VDD

with a 1MΩ (typical) resistor.

End of Conversion Output. A high-to-low transition of the EOC pulse can be used to latch the Parallel

Digital Output (pins D[11...0]).

Parallel Digital Output - bit 0 (LSB)

Parallel Digital Output - bit 1

Parallel Digital Output - bit 2

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