RS5C372A Просмотр технического описания (PDF) - RICOH Co.,Ltd.

Номер в каталоге

Компоненты Описание

Список матч

RS5C372A

I2C bus SERIAL INTERFACE REAL-TIME CLOCK ICs

RICOH Co.,Ltd. 

RS5C372A/B

7.3 Read Operation from Clock and Calendar Counters

Start condition

Read from clock and

calendar counters

*1

Stop condition

*2

*1) When reading from clock and calendar counters, do not insert

stop condition until all times from second to year have been

read to prevent error in reading time.

*2) Take care so that process from start condition to stop condi-

tion will be completed within 0.5 seconds. (The RS5C372A/B

force access to the CPU to terminate within 0.5 to 1.0 sec-

onds after start condition has occurred in case the CPU is

failed during access.)

7.4 Second Digit Adjustment by ±30 seconds

Control register 2←(00×1×111) *1

*1) Write 1 to the ADJ bit. (The ±30 seconds of adjustment is

made within 122.1µs (125µs when 32.000kHz crystal is used)

after the ADJ bit is set to 1.)

7.5 Interrupt Operation

7.5-1 Periodic Interrupt Operation

Set periodic interrupt

cycle select bit and

*1

interrupt output select bit

Interrupt to CPU

CTFG=1?

YES

Periodic interrupt operation

*2

Control register 2←(00×××011)

NO

Other

interrupt

operation

*1) The level mode is used for the periodic interrupt cycle select

bit.

*2) Interrupt to the CPU is cancelled by setting the CTFG bit to 0.

52

Share Link: