RS5C372A Просмотр технического описания (PDF) - RICOH Co.,Ltd.

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RS5C372A

I2C bus SERIAL INTERFACE REAL-TIME CLOCK ICs

RICOH Co.,Ltd. 

7. Typical Software-based Operations

7.1 Initialization upon Power-on

Start

*1

Power-on

NO

XSTP=1?

*3

YES

*4

Control register2←(00××××××)

*5

Set clock and calendar

counters and interrupt cycles

*2

ACK not returned or

Read Data is FFh

RS5C372A/B

*1) Start access after waiting one to two seconds that are required for starting up of oscillation and internal initialization after power on from 0V.

* * 2) If access is tried during IC internal initialization period described in 1, acknowledge signal may not be output, it is output only at first, or values read may

FFh. If any of these occurs, repeat accessing. This will be required also for ordinary routines when accessing may require 0.5 seconds or more.

*3) When XSTP=0 in oscillation halt sensing, it indicates power has not been booted from 0V but from back up supply.

*4) The XSTP shall be set to 0 by setting any data to the control register 2.

*5) Perform ordinary initial setting including clock calendar or interrupt cycle.

7.2 Write Operation to Clock and Calendar Counters

Start condition

Write to clock and

calendar counters

*1

Stop condition

*2

*1) When writing to clock and calendar counters, do not insert

stop condition until all times from second to year have been

written to prevent error in writing time.

*2) Take care so that process from start condition to stop condi-

tion will be completed within 0.5 seconds. (The RS5C372A/B

force access to the CPU to terminate within 0.5 to 1.0 sec-

onds after start condition has occurred in case the CPU is

failed during access.)

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