RS5C372A-E2 Просмотр технического описания (PDF) - RICOH Co.,Ltd.

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RS5C372A-E2

I2C bus SERIAL INTERFACE REAL-TIME CLOCK ICs

RICOH Co.,Ltd. 

RS5C372A/B

2.2-5 CTFG

Periodic Interrupt Flag Bit

CTFG

Description

0

Periodic interrupt output=OFF (“H”)

1

Periodic interrupt output=ON (“L”)

(Default)

This bit is set to “1” when periodic interrupt pulses are output (INTRA or INTRB=“L”) *1.

The CTFG bit may be set only to “0” in the interrupt level mode. Setting this bit to “0” sets either the INTRA or the

INTRB to OFF (“H”)*2. When this bit is set to “1” nothing happens.

*1) INTR=“L” for the RS5C372B.

*2) INTR=OFF (“H”) for the RS5C372B.

2.2-6 AAFG, BAFG

Alarm_A (Alarm_B) Flag Bit

AAFG, BAFG

Description

0

Unmatched alarm register with clock counter

(Default)

1

Matched alarm register with clock counter

· The alarm interruption is enabled only when the AALE, BALE bits are set to “1”. This bit turns to “1” when

matched time is sensed for each alarm.

· The AAFG, BAFG bit may be set only to “0”. Setting this bit to “0” sets either the INTRA or the INTRB to the OFF

“H”. When this bit is set to “1” nothing happens.

· When the AALE, BALE bit is set to “0”, alarm operation is disabled and “0” is read from the AAFG, BAFG bit.

*) INTR to the OFF (“H” ) for the RS5C372B.

Output Relationships Between the ALFG Bit and INTRA or INTRB (INTR for the RS5C372B)

AAFG (BAFG) bit

INTRA or INTRB pins

(INTR pin for the RS5C372B)

Setting of the AAFG

(BAFG) bit to 0

(Matched alarm time) (Matched alarm time)

Setting of the AAFG

(BAFG) bit to 0

(Matched alarm time)

20

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