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RS5C372A-E2

I2C bus SERIAL INTERFACE REAL-TIME CLOCK ICs

RICOH Co.,Ltd. 

RS5C372A/B

2.1-4 CT2, CT1, CT0

Periodic interrupt cycle select bit

CT2 CT1 CT0

Wave Form Mode

Description

Cycle and Falling Timing

0

0

0

—

off (“H”)

(Default)

0

0

1

—

Fixed at “L”

0

1

0 Pulse Mode 2Hz (Duty50%)

0

1

1 Pulse Mode 1Hz (Duty50%)

1

0

0 Level Mode Every second (synchronized with second count up)

1

0

1 Level Mode Every minute (00 second of every minute)

1

1

0 Level Mode Every hour (00 minute(s) 00 second(s) of every hour)

1

1

1 Level Mode Every month (the 1st day 00 A.M. 00 minute(s) 00 second(s) of every month)

1) Pulse mode : Outputs 2Hz, 1Hz clock pulses. For relationships with counting up of seconds see the diagram

below.

*) When 32.000kHz crystal is used,

In the 2Hz clock pulse mode, 0.496s clock pulses and 0.504s clock pulse are output alternately.

Duty cycle for 1Hz clock pulses becomes 50.4% (“L” duration is 0.496s while “H” duration is 0.504s).

2) Level mode : One second, one minute or one month may be selected for an interrupt cycle. Counting up of sec-

onds is matched with falling edge of interrupt output.

3) When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds.

Pulse mode : “L” duration of output pulses may change in the maximum range of ±3.784ms (±3.875ms when

32.000kHz crystal is used.)

For example, Duty will be 50±0.3784% (or 50±0.3875% when 32.000kHz crystal is used) at 1Hz.

Level mode : Frequency in one second may change in the maximum range of ±3.784ms (±3.875ms when

32.000kHz crystal is used.)

Relation Between Mode Waveforms and CTFG Bit

• Pulse mode

CTFG bit

INTRA or INTRB pins

(INTR pin for the RS5C372B)

Approx. 92µs (32.768kHz crystal is used)

Approx. 94µs (32.000kHz crystal is used)

(Counting up of seconds)

*) Since counting up of seconds and the falling edge has a time lag of approx. 92µs (at 32.768kHz) (approx. 94µs when 32.000kHz crystal is used), time

with apparently approx. one second of delay from time of the real-time clock may be read when time is read in synchronization with the falling edge of

output.

17

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