T8100-BAL Просмотр технического описания (PDF) - Agere -> LSI Corporation
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T8100-BAL Datasheet PDF : 92 Pages
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Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
1 Product Overview (continued)
1.3 Pin Information (continued)
Table 1. Pin Descriptions: Clocking and Framing Pins (continued)
Symbol
/C4
C2
SCLK
SCLKX2
L_SC[3:0]
FGA[5:0]
FGA[11:6]
FGB[5:0]
FGB[11:6]
PRIREFOUT
PLL1VDD
PLL1GND
EN1
4MHZIN
PLL2VDD
PLL2GND
EN2
3MHZIN
XTALIN
XTALOUT
TCLKOUT
Pin
104
106
110
108
36—33
94—99
87—92
80—85
73—78
58
53
51
55
54
208
206
3
1
47
48
203
Ball
U16
T17
R17
P15
M3, N1, M2, M1
R12, T13, U14, P12,
R13, T14
T11, P11, R11, U12,
T12, U13
U9, R9, U10, T10,
R10, U11
U6, T7, R8, U7, T8,
U8
P5
U1
No ball for this
signal, internally
connected.
T3
U2
A2
No ball for this
signal, internally
connected.
C2
A1
R2
T1
C4
Type
Name/Description
I/O MVIP 4.096 MHz Clock. 8 mA drive, Schmitt in, 50 kΩ
internal pull-up.
I/O MVIP 2.048 MHz Clock. 8 mA drive, Schmitt in, 50 kΩ
internal pull-up.
I/O SC-Bus 2/4/8 MHz Clock. 24 mA drive, Schmitt in, 50 kΩ
internal pull-up.
I/O SC-Bus Inverted 4/8 MHz Clock (Active-Low). 24 mA
drive, Schmitt in, 50 kΩ internal pull-up.
O Local Selected Clocks. 1.024 MHz, 2.048 MHz,
4.096 MHz, 8.192 MHz, 16.384 MHz, frame (8 kHz), or sec-
ondary (NETREF). 8 mA drive, 3-state.
O Frame Group A. 8 mA drive, 3-state.
O Frame Group B. 8 mA drive, 3-state.
O Output from Primary Clock Selector/Divider. 8 mA drive.
— PLL #1 VCO Power. This pin must be connected to power,
even if PLL #1 is not used.
— PLL #1 VCO Ground. This pin must be connected to
ground, even if PLL #1 is not used.
I PLL #1 Enable. Requires cap to VSS to form power-on
reset, or may be driven with RESET line. 50 kΩ internal
pull-up.
I PLL #1 Rate Multiplier. Can be 2.048 MHz or 4.096 MHz.
50 kΩ internal pull-up.
— PLL #2 VCO Power. This pin must be connected to power
if PLL #2 is not used and 3MHZIN is used. Can be left float-
ing only if both PLL #2 and 3MHZIN are not used.
— PLL #2 VCO Ground. This pin must be connected to
ground if PLL #2 is not used and 3MHZIN is used. Can be
left floating only if both PLL #2 and 3MHZIN are not used.
I PLL #2 Enable. Requires cap to VSS to form power-on
reset, or may be driven with RESET line. 50 kΩ internal
pull-up.
I PLL #2 Rate Multiplier. Input, 50 kΩ internal pull-up.
I 16.384 MHz Crystal Connection or External Clock
Input.
O 16.384 MHz Crystal, Feedback Connection.
O Selected output to drive framers. 8 mA drive, 3-state.
Lucent Technologies Inc.
7
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