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T8100-BAL

Ambassador™ T8100 H.100/H.110 Interface and Time-Slot Interchanger

Agere -> LSI Corporation 

Preliminary Data Sheet

August 1998

Ambassador T8100

H.100/H.110 Interface and Time-Slot Interchanger

Table of Contents (continued)

Contents

Page

5 Outline Diagram......................................................78

5.1 208-Pin Square Quad Flat Package (SQFP) ...78

5.2 217-Pin Ball Grid Array (PBGA) ......................79

6 Ordering Information...............................................79

Appendix A. Application of Clock Modes...................80

Appendix B. Minimum Delay and Constant Delay

Connections ...........................................86

B.1 Connection Definitions .....................................86

B.2 Delay Type Definitions ....................................87

B.2.1 Exceptions to Minimum Delay.....................88

B.2.2 Lower Stream Rates ...................................88

B.2.3 Mixed Minimum/Constant Delay .................89

Figures

Page

Figure 1. Pin Diagram .................................................5

Figure 2. 217 PBGA—Top View .................................6

Figure 3. Block Diagram of the T8100 ......................13

Figure 4. Local Bus Section Function .......................21

Figure 5. Local Bus Memory Connection Modes ......22

Figure 6. Local Streams, Memory Structure .............24

Figure 7. Local Memory, Fill Patterns .......................25

Figure 8. Simplified Local Memory State Timing,

65.536 MHz Clock ...................................28

Figure 9. CAM Architecture ......................................30

Figure 10. Simplified H-Bus State Timing,

65.536 MHz Clock ...................................32

Figure 11. Illustration of CAM Cycles .......................34

Figure 12. Clocking Section ......................................37

Figure 13. A, B, and C Clock Fallback State

Diagram ..................................................40

Figure 14. Frame Group Output Options ..................49

Figure 15. External Connection to PLLs ...................55

Figure 16. Physical Connections for H.110 ..............56

Figure 17. Local-to-Local Connection

Programming ..........................................58

Figure 18. CAM Programming, H-Bus-to-Local

Connection ..............................................60

Figure 19. Clock Alignment ......................................69

Figure 20. Frame Diagram .......................................70

Figure 21. Detailed Timing Diagram .........................71

Figure 22. Detailed Clock Skew Diagram .................73

Figure 23. ac Electrical Characteristics, Local

Streams, and Frames .............................74

Figures

Page

Figure 24. Microprocessor Access Intel Multi-

plexed Write Cycle ................................. 75

Figure 25. Microprocessor Access Intel Multi-

plexed Read Cycle ................................. 75

Figure 26. Microprocessor Access Motorola

Write Cycle ............................................. 76

Figure 27. Microprocessor Access Motorola

Read Cycle ............................................ 76

Figure 28. Microprocessor Access Intel

Demultiplexed Write Cycle ..................... 77

Figure 29. Microprocessor Access Intel

Demultiplexed Read Cycle ..................... 77

Figure 30. E1, CT Bus Master, Compatibility Clock

Master, Clock Source = 2.048 MHz

from Trunk .............................................. 81

Figure 31. T1, CT Bus Master, Compatibility Clock

Master, Clock Source = 1.544 MHz

from Trunk .............................................. 82

Figure 32. E1, Slave to CT Bus, Clock Source Is

Either a 16 MHz or a 4 MHz or a

2 MHz and Frame, NETREF

Source = 2.048 MHz from Trunk ............ 83

Figure 33. T1, Slave to CT Bus, Clock Source Is

Either a 16 MHz or a 4 MHz or a

2 MHz and Frame, NETREF Source

= 1.544 MHz from Trunk ........................ 84

Figure 34. Constant Delay Connections,

CON[1:0] = 0X ........................................ 87

Figure 35. Minimum Delay Connections,

CON[1:0] = 0X ........................................ 88

Figure 36. Mixed Minimum/Constant Delay Con-

nections, CON[1:0 = 10] ......................... 89

Figure 37. Extended Linear (Mixed Minimum/Con-

stant) Delay, CON[1:0] = 11 ................... 90

Lucent Technologies Inc.

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