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T8100-BAL

Ambassador™ T8100 H.100/H.110 Interface and Time-Slot Interchanger

Agere -> LSI Corporation 

Ambassador T8100

H.100/H.110 Interface and Time-Slot Interchanger

Preliminary Data Sheet

August 1998

Table of Contents

Contents

Page

1 Product Overview .....................................................1

1.1 Introduction ........................................................1

1.2 Features .............................................................1

1.3 Pin Information ...................................................5

1.4 Enhanced Local Stream Addressing ................10

1.5 Full H.100 Stream Address Support ................10

1.6 Onboard PLLs and Clock Monitors ..................11

1.7 Phase Alignment of Referenced and

Generated Frames ...........................................11

1.8 Interfaces .........................................................11

1.8.1 Microprocessors ..........................................11

1.8.2 Framing Groups ..........................................11

1.8.3 General-Purpose Register and I/O..............11

1.9 Applications ......................................................11

1.10 Application Overview .....................................11

2 Architecture and Functional Description.................12

2.1 Register/Memory Maps ....................................14

2.1.1 Main Registers ............................................14

2.1.2 Master Control and Status Register ............14

2.1.3 Address Mode Register...............................15

2.1.4 Control Register Memory Space .................16

2.2 Local Bus Section ............................................21

2.2.1 Constant Frame Delay and Minimum

Delay Connections ......................................22

2.2.2 Serial and Parallel .......................................23

2.2.3 Data Rates and Time-Slot Allocation ..........23

2.2.4 LBS: Local Stream Control, 0x0C ...............27

2.2.5 State Counter Operation .............................28

2.3 H-Bus Section ..................................................29

2.3.1 Memory Architecture ...................................29

2.3.2 CAM Operation and Commands .................31

2.3.3 H-Bus Access..............................................35

2.3.4 L-Bus Access ..............................................36

2.3.5 H-Bus Rate Selection and Connection

Address Format...........................................36

2.4 Clocking Section ..............................................36

2.4.1 Clock and NETREF Selection .....................38

2.4.2 Dividers and Rate Multipliers.......................38

2.4.3 State Machines ...........................................39

2.4.4 Bit Sliding (Frame Locking) .........................39

2.4.5 Clock Fallback .............................................39

2.4.6 Clock Control Register Definitions...............41

2.4.7 CKMD, CKND, CKRD: Clocks, Main,

NETREF, Resource Dividers, 0x07, 0x08,

and 0x09 .....................................................46

2.5 Interface Section ..............................................46

2.5.1 Microprocessor Interface.............................46

2.5.2 General-Purpose Register...........................47

2.5.3 Framing Groups ..........................................47

2.6 Error Registers .................................................50

2.7 The JTAG Test Access Port ............................51

2.7.1 Overview of the JTAG Architecture .............51

2.7.2 Overview of the JTAG Instructions..............51

2

Contents

Page

2.7.3 Elements of JTAG Logic............................. 52

2.8 Testing and Diagnostics .................................. 53

2.8.1 Testing Operations ..................................... 53

2.8.2 Diagnostics................................................. 53

3 Using the T8100 .................................................... 55

3.1 Resets ............................................................. 55

3.1.1 Hardware Reset ......................................... 55

3.1.2 Software Reset........................................... 55

3.1.3 Power-On Reset......................................... 55

3.2 Basic Connections .......................................... 55

3.2.1 Physical Connections for H.110 ................. 56

3.2.2 H.100 Data Pin Series Termination............ 56

3.2.3 PC Board Considerations........................... 56

3.3 Using the LAR, AMR, and IDR for

Connections .................................................... 57

3.3.1 Setting Up Local Connections .................... 57

3.3.2 Setting Up H-Bus Connections................... 59

3.3.3 Programming Examples ............................. 62

3.2.4 Miscellaneous Commands ......................... 65

4 Electrical Characteristics ....................................... 66

4.1 Absolute Maximum Ratings ............................ 66

4.2 Handling Precautions ...................................... 66

4.3 Crystal Oscillator ............................................. 67

4.4 dc Electrical Characteristics, H-Bus

(ECTF H.100 Spec., Rev. 1.0) ........................ 67

4.4.1 Electrical Drive Specifications—CT_C8

and /CT_FRAME ........................................ 67

4.5 dc Electrical Characteristics, All Other Pins .... 68

4.6 H-Bus Timing (Extract from H.100

Spec., Rev. 1.0) .............................................. 69

4.6.1 Clock Alignment ........................................ 69

4.6.2 Frame Diagram .......................................... 70

4.6.3 Detailed Timing Diagram............................ 71

4.6.4 ac Electrical Characteristics, Timing,

H-Bus (H.100, Spec., Rev. 1.0).................. 72

4.6.5 Detailed Clock Skew Diagram.................... 73

4.3.6 ac Electrical Characteristics, Skew

Timing, H-Bus (H.100, Spec., Rev. 1.0) ..... 73

4.6.7 Reset and Power On .................................. 73

4.7 ac Electrical Characteristics, Local

Streams, and Frames ...................................... 74

4.8 ac Electrical Characteristics, Micro-

processor Timing ............................................. 75

4.8.1 Microprocessor Access Intel Multiplexed

Write and Read Cycles............................... 75

4.8.2 Microprocessor Access Motorola Write

and Read Cycles ........................................ 76

4.8.3 Microprocessor Access Intel Demultiplexed

Write Cycle ................................................. 77

Lucent Technologies Inc.

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