RMWB24001 Просмотр технического описания (PDF) - Fairchild Semiconductor
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RMWB24001 Datasheet PDF : 7 Pages
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Electrical Characteristics (At 25°C), 50Ω system, Vd = +4V, Quiescent Current Idq = 70mA
Parameter
Frequency Range
Gate Supply Voltage1 (Vg)
Gain (Small Signal Pin = 10dBm)
Gain Variation vs. Frequency
Power Output Saturated: (Pin = +5dBm)
Drain Current at Psat
Power Added Efficiency (PAE): at Psat
Input Return Loss (Pin = -10dBm)
Output Return Loss (Pin = -10dBm)
DC Detector Voltage at Pout = 17dBm
Min
Typ
Max
17
24
-0.2
13
15
18
2.0
14
17
19
80
15
12
12
1.0
Note:
1: Typical range of gate voltage is -0.5 to 0V to set typical Idq of 70mA.
Units
GHz
V
dB
dB
dBm
mA
%
dB
dB
V
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE.
Chip carrier material should be selected to have GaAs compatible thermal coefficient of expansion and high thermal
conductivity such as copper molybdenum or copper tungsten. The chip carrier should be machined, finished flat, plated with
gold over nickel and should be capable of withstanding 325°C for 15 minutes.
Die attachment should utilize Gold/Tin (80/20) eutectic alloy solder and should avoid hydrogen environment for PHEMT
devices. Note that the backside of the chip is gold plated and is used as RF and DC ground.
These GaAs devices should be handled with care and stored in dry nitrogen environment to prevent contamination of
bonding surfaces. These are ESD sensitive devices and should be handled with appropriate precaution including the use of
wrist grounding straps. All die attach and wire/ribbon bond equipment must be well grounded to prevent static discharges
through the device.
Recommended wire bonding uses 3 mils wide and 0.5 mil thick gold ribbon with lengths as short as practical allowing for
appropriate stress relief. The RF input and output bonds should be typically 0.012" long corresponding to a typical 2 mil gap
between the chip and the substrate material.
DRAIN
SUPPLY
Vd1
DRAIN
SUPPLY
Vd2 and Vd3
OUTPUT POWER
DETECTOR VOLTAGE
Vdet
MMIC CHIP
RF IN
RF OUT
GROUND GATE SUPPLY
(Back of Chip)
Vg
Figure 1. Functional Block Diagram1
Note:
1: Detector delivers >0V DC into 3kΩ load resistor for > +17dBm output power. If output power level detection is not desired, do not make connection to detector
bond pad.
©2004 Fairchild Semiconductor Corporation
RMWB24001 Rev. D
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