M65762FP Просмотр технического описания (PDF) - Renesas Electronics

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M65762FP

QM-Coder

Renesas Electronics 

M65762FP

(8) Processing line count register (R)

(Address: 8)

d7

d0

LIN_REG_L:

LINE_L

(Address: 9)

LIN_REG_H:

LINE_H

d0 to 7 (LINE_L):

d0 to 7 (LINE_H):

Read out the number of lines actually processed (Low byte) (0 to 65535)

Read out the number of lines actually processed (Upper byte)

The number of processed lines number of set lines, coding/decoding/through processing stop

temporary/end of processing.

Note: The number of lines in this process is cleared to 0 with the processing start command

issued.

(9) Buffer register (W/R)

(Address: A)

d7

d0

DWR_BUF:

DWR

d0 to 7 (DWR):

Data for loading/storing context table RAM

This register is a buffer for loading data into the context table RAM via the host bus or for

storing data outside. After issuance of load/store start command of the context table RAM

(command register d3 = 1), this register is available to start loading or storing data. Prediction

value (MPS) and prediction unmatched probability (LSZ) can be stored in context table RAM

for a unit of 1024 contexts in total. Figure 4 and table 4 provide the address assignment of

context table RAM and the data bit array.

Since context table RAM is 2-byte data, access is gained alternately in order from low byte to

upper byte. Each time two-byte access is gained, the RAM address is automatically

incremented (sequential access from address 0).

Notes: 1. Data is not allowed to be loaded and stored at a time. Random access to RAM is

not allowed.

2. Only 133 types specified by the JBIG international standard (see " Appendix A.2")

are allowed to be specified for the LSZ value. (For example, load '5a1d' for

initialization.)

876

54329

10?

3-line template

854329

7610?

2-line template

Figure 4 Address Assignment of Context Table RAM

(Number for Address Bit (LSB: 0, MSB: 9), MSB: 9 for AT Pixel)

Table 4 Data Bit Array of Context Table RAM

High Order Byte

Low Order Byte

d15

d14

•••••

d8

d7

•••••

d0

MPS

L14

•••••

L8

L7

•••••

L0

Note: MPS: Prediction value MPS (0/1)

L14 to 0: Low 15 bits of prediction unmatched probability LSZ ('0001' to '5b12')

REJ03F0235-0200 Rev.2.00 Sep 14, 2007

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