M65762FP Просмотр технического описания (PDF) - Renesas Electronics

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M65762FP

QM-Coder

Renesas Electronics 

M65762FP

(4) Status register (R)

(Address: 2)

d7

STAT_REG:

0

d5

d0

PS

SC

IS

MS

DS

JS

d0 (JS):

d1 (DS):

d2 (MS):

d3 (IS):

d4 (SC):

d5 (PS):

Processing (initialization/coding/decoding/through) status

(0: Processing in progress (temporary stop or initial), 1: Completion of processing)

This JS bit is set to 1 in the following cases: when the initialization is complete with the RAM

initialization command issued (IC = 1), when all coding data is read completely at time of coding with

the start command of termination end processing issued (JC = 1, JP = 0), and when all image data is read

completely at time of image data through and at time of decoding. When the temporary stop processing

start command is issued (JC = 1, JP = 1), this JS bit remains to be 0, even if the process for the number

of setup lines ends. (However, an interruption occurs at time of temporary stop.)

Ready for reading/writing coding data (image data case of the through mode) on the code data bus

(1: Ready, 0: Read/write disabled)

When this bit is set to 1, data can be read/written on the code data bus. (This bit is equivalent to the

CDRQ pin.)

Detects marker code at time of decoding (0: Not detected, 1: Detected)

This bit is set to 1 when some marker code is detected at time of decoding.

Status of interrupt request (INTR pin) (0: Not requested, 1: Requested)

SC count-over error at time of coding (0: Normal, 1: Occurrence of SC counter overflow)

Note: The SC counter is a counter for consecutive "FF" data bytes generated in the coding process.

Though coding process continues if the SC counter overflows, normal coding data is not output

(encoding error).

Processing (temporary stop/termination end) mode

(1: Temporary stop processing mode, 0: Termination end processing mode)

This PS bit corresponds to the selection of process temporary stop/termination end of the d3 (JP) bit of

command register.

(5) Interrupt enable register (W/R)

(Address: 3)

d7

IENB_REG:

MP

0

d3

d0

SE

ME

DE

JE

d0 (JE):

d1 (DE):

d2 (ME):

d3 (SE):

Processing (initialization/coding/decoding/through)

Temporary stop/termination end interrupt (0: Interrupt mask, 1: Interrupt enable)

Coding data (image data) read/write ready interrupt (0: Interrupt mask, 1: Interrupt enable)

Marker code detection interrupt at time of decoding (0: Interrupt mask, 1: Interrupt enable)

SC count-over error interrupt at time of coding (0: Interrupt mask, 1: Interrupt enable)

Note:

Bits d0 to d3 are interrupt enable of bits d0 to d2 and d4 corresponding to the status register.

When one of the status bits set to interrupt enable is set to 1, the interrupt request signal (INTR)

is asserted (for d0 (JE), an interrupt occurs even at the time of temporary stop).

When the status is set to 0 by H/W reset etc., or when interrupt factor is eliminated by

interruption masking, INTR is negated. The status register is not cleared by occurrence of

interruption or by R/W of interruption enable register.

REJ03F0235-0200 Rev.2.00 Sep 14, 2007

Page 12 of 34

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