M65762FP Просмотр технического описания (PDF) - Renesas Electronics

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M65762FP

QM-Coder

Renesas Electronics 

M65762FP

4. Register Setting Sequence

(1) Initialization sequence of built-in line memory and context table RAM

This sequence is used to carry out initialization sequence (0 clear) of context table RAM after the initialization (Note)

of the built-in line memory by H/W reset.

When the initialization is unnecessary (the contents of the current status table are directly used), this sequence is

unnecessary.

1

H/W Reset

Context mode set up

Issue context table RAM

initialization command

d7

d0

SYS_REG: 0 0 0 0 0 0 0 1

; H/W reset bit ON

SYS_REG: 0 0 0 0 0 0 0 0

; H/W reset bit OFF

* Period of H/W reset bit set to ON (time from when d0 = "1"

is written until d0 = "0" is written) requires 100 ns or more.

CMD_REG: 0 0 0 0 0 0 0 1

; Initializes context table RAM

Set interrupt enable

IENB_REG: 0 0 0 0 0 0 0 1

; Process end interrupt enable

Context table RAM is initialized (0 clear) in this period.

The number of clocks required for initialization is as follows:

1024 + a [Clock]

(Occurrence of interrupt)

Set interrupt disable

d7

d0

IENB_REG: 0 0 0 0 0 0 0 0

; Interrupt disable

Read out status register

(check the end of processing)

STAT_REG: − − − − − − − j

; j = End of processing

j=1?

Y

N

(Error)

End of initialization command

2 To 2)

CMD_REG: 0 0 0 0 0 0 0 0

; End of initialization

Note: Line memory is initialized by H/W reset to prepare the all white (0) data as a reference line to provide

for the start of coding/decoding process and to initialize LNTP bit (LNTP = 1) for typical prediction.

REJ03F0235-0200 Rev.2.00 Sep 14, 2007

Page 18 of 34

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