M65761FP Просмотр технического описания (PDF) - Renesas Electronics

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M65761FP

QM-Coder

Renesas Electronics 

M65761FP

Description of Registers

(1) System set up register (W/R)

(Address: 0)

d7 (MSB)

d0

SYS_REG:

PB

PI

BX

BS

CX

MOD

HR

d0 (HR):

d1, d2 (MOD):

d3 (CX):

d4 (BS):

d5 (BX):

H/W reset (0: Active, 1: Reset state)

To make a H/W reset, set this bit to 1 then to 0.

Reset initializes the entire LSI including the group of register and line memory. However, the

context table RAM is not initialized.

This sets up the operating modes.

(d2 = 0, d1 = 0: coding, d2 = 1, d1 = 0: lage data through (lage data I/F Host I/F),

d2 = 0, d1 = 1: decoding, d2 = 1, d1 = 1: lage data through (Host I/F lage data I/F))

Context select (0: internal context, 1: Image data through)

Note: The internal context should be selected when the image data through mode is used.

When initializing or processing R/W of the context table RAM and coding/decoding.

This bit must be set the same. (Because RAM configuration changes depending on

internal/external modes.)

Select data bit swap of the host bus. (0: MSB (d7) first, 1: LSB (d0) first)

Select data byte swap of the host bus. (0: Lower byte (A) first, 1: Upper byte (B) first)

Note: BX is valid only when the host bus is 16 bits. (BUS16 = HIGH)

Table 1 The Coed Data and Image Data Lineup on the Host Bus

Bus Width

BUS16

Swap

BX

BS

Upper Address (B)

d15

•••••

d8

Lower Address (A)

d7

•••••

d0

1

0

0

b8

•••••

b15

b0

•••••

b7

16-bit

0

1

b15

•••••

b8

b7

•••••

b0

1

0

b0

•••••

b7

b8

•••••

b15

1

1

b7

•••••

b0

b15

•••••

b8

0

—

0

—

b0

•••••

b7

8-bit

—

1

—

b7

•••••

b0

Note: b0 is the first coded data on the time series/the left-hand side image data on the screen.

b15 is the last coded data on the time series/the right-hand image data on the screen.

b6 (PI):

b7 (PB):

Selects the image data I/O I/F (0: Serial I/F, 1: Parallel I/F)

Selects the bit width of the image data bus (0: 32-bit bus (PD0 to 31), 1: 16-bit bus (PD0 to 15))

Table 2 The Image Data Lineup on the Image Data Parallel Bus

Bit Width

PD31

•••••

PD16

PD15

•••••

PD0

PB = 0

p0

•••••

p15

p16

•••••

p31

PB = 1

—

p0

•••••

p15

Note: p0 is the image data on the left-hand on the screen.

p31 is the image data on the right-hand on the screen.

REJ03F0234-0200 Rev.2.00 Sep 14, 2007

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