CY62146VLL-70ZI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY62146VLL-70ZI Datasheet PDF : 12 Pages
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CY62146V MoBL™
Switching Characteristics Over the Operating Range[5]
70 ns
Parameter
Description
Min.
Max.
Unit
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
WRITE CYCLE[8, 9]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6, 7]
OE HIGH to High Z[7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
70
ns
70
ns
10
ns
70
ns
25
ns
5
ns
20
ns
10
ns
20
ns
0
ns
70
ns
35
ns
5
ns
20
ns
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-Up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
40
ns
tBW
BHE / BLE Pulse Width
60
ns
tSD
Data Set-Up to Write End
30
ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[6, 7]
WE HIGH to Low Z[6]
0
ns
25
ns
10
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
5
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