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CY62146VLL-70ZI

256K x 16 Static RAM

Cypress Semiconductor 

1*C Y6214 6V

MoBL™

CY62146V MoBL™

Features

• Low voltage range:

— CY62146V: 2.7V–3.6V

• Ultra-low active, standby power

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

Functional Description

The CY62146V is a high-performance CMOS static RAM or-

ganized as 262,144 words by 16 bits. These devices feature

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL™) in por-

table applications such as cellular telephones. The device also

has an automatic power-down feature that significantly reduc-

es power consumption by 99% when addresses are not tog-

gling. The device can also be put into standby mode when

deselected (CE HIGH). The input/output pins (I/O0 through

Logic Block Diagram

DATA IN DRIVERS

A9

A8

A7

A6

A5

256K x 16

A4

RAM Array

A3

2048 x 2048

A2

A1

A0

COLUMN DECODER

256K x 16 Static RAM

I/O15) are placed in a high-impedance state when: deselected

(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is

written into the location specified on the address pins (A0

through A16). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O8 through I/O15) is written into the location

specified on the address pins (A0 through A17).

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins

will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,

then data from memory will appear on I/O8 to I/O15. See the

truth table at the back of this data sheet for a complete descrip-

tion of read and write modes.

The CY62146V is available in 48-Ball FBGA and standard

44-Pin TSOP Type II (forward pinout) packaging.

I/O0–I/O7

I/O8–I/O15

BHE

WE

CE

OE

BLE

Pin Configurations

TSOP II (Forward)

Top View

A4 1

A3 2

A2 3

A1 4

A0 5

CE 6

I/O0 7

I/O1 8

I/O2 9

I/O3 10

VCC 11

VSS 12

I/O4 13

I/O5 14

I/O6 15

I/O7 16

WE 17

A16 18

A15 19

A14 20

A13 21

A12 22

44 A5

43 A6

42 A7

41 OE

40 BHE

39 BLE

38 I/O15

37 I/O14

36 I/O13

35 I/O12

34 VSS

33 VCC

32 I/O11

31 I/O10

30 I/O9

29 I/O8

28 NC

27 A8

26 A9

25 A10

24 A11

23 A17

MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

June 15, 2001

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