CS7654 Просмотр технического описания (PDF) - Cirrus Logic

Номер в каталоге

Компоненты Описание

Список матч

CS7654

CCD Color-Space Processor with Analog Output

Cirrus Logic 

CS7654

Following the luma delay, the data is passed

through an interpolation filter that has a program-

mable bandwidth, followed by a variable gain am-

plifier in which the luma dc values are modifiable

via the Y_AMP Register.

The output of the luma amplifier connects to the

sync insertion block. Sync insertion is accom-

plished by multiplexing, into the luma data path,

the different sync dc values at the appropriate

times. The digital sync generator takes horizontal

sync and vertical sync timing signals and generates

the appropriate composite sync timing (including

vertical equalization and serration pulses), blank-

ing information, and burst flag. The sync edge rates

conform to RS-170A or ITU R.BT601 and ITU

R.BT470 specifications.

It is also possible to delay the luminance signal,

with respect to the chrominance signal, by up to

three pixel clocks. This variable delay is useful to

offset different propagation delays of the luma

baseband and modulated chroma signals. This ad-

justable luma delay is available only on the

COMP_VID output.

Digital to Analog Converters

The CS7654 provides three discrete 27 MHz DACs

for analog video. The default configuration is one

10-bit DAC for S-video chrominance, one 10-bit

DAC for S-Video luminance, one 10-bit DAC for

composite output. All three DACs are designed for

driving either low-impedance loads (double termi-

nated 75 Ω) or high-impedance loads (double ter-

minated 300 Ω).

The DACs can be put into tri-state mode via host-

addressable control register bits. Each of the six

DACs has its own associated DAC enable bit. In

the Disable Mode, the 10-bit DACs source (or sink)

zero current.

For lower power standby scenarios, the CS7654

also provides power shut-off control for the DACs.

Each DAC has an associated DAC shut-off bit.

Voltage Reference

The CS7654 is equipped with an on-board voltage

reference generator (1.232 V) that is used by the

DACs. The internal reference voltage is accurate

enough to guarantee a maximum of 3% overall gain

error on the analog outputs. However, it is possible

to override the internal reference voltage by apply-

ing an external voltage source to the VREF pin.

Current Reference

The DAC output current-per-bit is derived in the

current reference block. The current step is speci-

fied by the size of resistor placed between the

ISET_DAC current reference pin and electrical

ground.

A 4 kΩ resistor needs to be connected between

ISET_DAC pin and GND. The DAC output cur-

rents are optimized to either drive a doubly termi-

nated load of 75 Ω (low impedence mode) or a

double terminated load of 300 Ω (high impedence

mode). The 2 output current modes are software se-

lectable through a register bit. Note that there are

two ISET pins on the device, one for the DACS,

and one for the PLL.

Closed Caption Insertion

The CS7654 is capable of NTSC Closed Caption

insertion on lines 21 and 284 independently.

Closed captioning is enabled for either one or both

lines via the CC_EN [1:0] Register bits and the

data to be inserted is also written into the four

Closed Caption Data registers. The CS7654, when

enabled, automatically generates the seven cycles

of clock run-in (32 times the line rate), start bit in-

sertion (001), and finally insertion of the two data

bytes per line. Data low at the video outputs corre-

sponds to 0 IRE and data high corresponds to 50

IRE.

There are two independent 8-bit registers per line

(CC_21_1 & CC_21_2 for line 21 and CC_284_1

& CC_284_2 for line 284). Interrupts are also pro-

vided to simplify the handshake between the driver

15

Share Link: