IDT29FCT52A Просмотр технического описания (PDF) - Integrated Device Technology
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IDT29FCT52A Datasheet PDF : 7 Pages
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IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500Ω
50pF
RT
500Ω
CL
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
2533 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
t SU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t SU
tH
t REM
tH
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
1.5V
tW
1.5V
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
tPLH
OUTPUT
t PLH
OPPOSITE PHASE
INPUT TRANSITION
t PHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3.5V
1.5V
1.5V
0V
DISABLE
tPLZ
3V
1.5V
0V
3.5V
tPHZ
0.3V V OL
0.3V V OH
0V
NOTES
2533 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.1
6
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