A64E06161(2004) Просмотр технического описания (PDF) - AMIC Technology
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A64E06161 Datasheet PDF : 20 Pages
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Page Mode Description
The Page Mode operation takes advantage of the fact that
adjacent address can be read in shorter period of time than
random addresses. Write operations do not support
comparable page mode functionality. The Page Mode
operation can be enabled and disabled in the CR register. If
the CR register bit A7 is set to a “1”, Page Mode operation is
enabled.
The A64E06161 provides following operation mode for
reducing power:
1. Deep Power Down (DPD) mode
2. Reduce Memory Size (RMS) mode
3. Partial Array Refresh (PAR) mode
4. Temperature Compensated Refresh (TCR) mode
1. Deep Power Down (DPD) mode
In this mode, the internal refresh is turned off and all data
integrity of the array is lost. Deep Power Down (DPD) mode
is entered by ZZ low and keep 10us with A4 register bit set
A64E06161
to a ” 0”. The device stays in the Deep Power Down (DPD)
mode until ZZ is driven High. If the A4 register bit is set
equal to “1”, Deep Power Down (DPD) mode will not be
activated. Once the A64E06161 exits the Deep Power Down
(DPD) mode, the content of the CR register is destroyed and
the CR register would go into the default state upon normal
operation.
2. Reduce Memory Size (RMS) mode
In this mode, the A64E06161 can be operated as a reduced
size device. For example, one can operate the 16M
A64E06161 as a 4M or 8M memory block. Reduce Memory
Size (RMS) mode can be enabled by having the appropriate
setting in the CR register. The mode is effective once ZZ
goes high and remains in the Reduce Memory Size (RMS)
mode until full array restored by setting the CR register
again. At power on, all four section of the device are
activated and the A64E06161 enter into its default state of
full memory size and refresh space.
Variable Address Space – Address Patterns
Partial Array Refresh Mode (A3 =0, A4 = 1)
A2 A1, A0
Refresh Section
Address
0
11 One-fourth of the Die
00000h - 3FFFFh (A19 = A18 = 0)
0
10 Half of the Die
00000h - 7FFFFh (A19 = 0)
0
01 Three-fourths of the Die 00000h - BFFFFh (A19 : A18 ≠ 11)
1
11 One-fourth of the Die
C0000h - FFFFh (A19 = A18 = 1)
1
10 Half of the Die
80000h - FFFFFh (A19 = 1)
1
01 Three-fourths of the Die 40000h - FFFFFh (A19: A18 ≠ 00)
Reduced Memory Size Mode (A3 = 1, A4 = 1)
0
11 One-fourth of the Die
00000h - 3FFFFh (A19 = A18 = 0)
0
10 Half of the Die
00000h - 7FFFFh (A19 = 0)
0
01 Three-fourths of the Die 00000h - BFFFFh (A19 : A18 ≠ 11)
1
11 One-fourth of the Die
C0000h - FFFFh (A19 = A18 = 1)
1
10 Half of the Die
80000h - FFFFFh (A19 = 1)
1
01 Three-fourths of the Die 40000h - FFFFFh (A19 : A18 ≠ 00)
Size
256K × 16
512K × 16
768K × 16
256K × 16
512K × 16
768K × 16
Density
4M
8M
12M
4M
8M
12M
256K × 16
4M
512K × 16
8M
768K × 16
12M
256K × 16
4M
512K × 16
8M
768K × 16
12M
PRELIMINARY (November, 2004, Version 0.1)
8
AMIC Technology, Corp.
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