A64E06161(2004) Просмотр технического описания (PDF) - AMIC Technology

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A64E06161
(Rev.:2004)

1M X 16 Bit Low Voltage Super RAM

AMIC Technology 

A64E06161

Configuration Register

The configuration register (CR) defines how the

A64E06161 operates and whether page mode read

accesses are permitted. The register is automatically

loaded with default setting during power on and can be

updated anytime while the device is operating in a normal

state.

CR Register Description

Reserved PAGE TCR ZZ Enable Deep Sleep Array On/Off on ZZ

A19 - A8 A7 A6 A5

A4

A3

PAR Top/Bottom

Selection

A2

PAR Memory Selection

A1

A0

Bit(s)

A19 - A8

7

6, 5

4

3

2

1-0

Name

Reserved

Page Mode on/off

Temperature Compensated Register

Section

ZZ Enable Deep Sleep

Array On/Off on ZZ

PAR Top/Bottom Half Selection

PAR Memory Selection

Deserved

Reserved, All must be set to “0”

0 - Page Mode Disabled (Default)

1 - Page Mode Enabled

11 - +85°C (Default)

00 - +70°C

01 - +45°C

10 - +15°C

0 - DPD Mode Enabled

1 - DPD Mode Disabled (Default)

0 - PAR Mode (Default)

1 - RMS Mode

0 - Bottom (Default)

1 - Top

01 - 3/4 Array (12M)

10 - 1/2 Array (8M)

11 - 1/4 Array (4M)

PRELIMINARY (November, 2004, Version 0.1)

6

AMIC Technology, Corp.

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