PRELIMINARY
ZR36015
SYSCLK
MWE
MOE
40
40
41
41
Figure 1. Memory Interface Synchronous Timing
SYSCLK
MADDR
MWE
MOE
MDATA (OUT)
MDATA (IN)
18
40
19
Write Address
21
30
Read Address
41
28
23
27
24
Write Data
33
37
35
34
Read Data
Figure 1. Memory Interface R/W Asynchronous Timing
SPH
ADDR
WR
RD
PXDATA (7:0)
53
54
Write Address
50
56
51
55
Write Address
59
60
Write Data
Write Data
Figure 1. System Interface Timing
58
Read Address
52
62
61
64
63
SYSCLK
9
CSCCLK
Figure 1. 203CLK Timing - Mode = 0
SYSCLK
9
CSCCLK
Figure 1. 203CLK Timing - Mode = 1, 2, 3
25