ZR36015 Просмотр технического описания (PDF) - Unspecified
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ZR36015 Datasheet PDF : 27 Pages
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PRELIMINARY
ZR36015
Signal
Number
Description
Min
Max Units Test Conditions
53
Host Address Setup
tbd
ns
54
Host Address Hold
tbd
ns
55
Minimum Non-Active Time Between Host Read or Write
tbd
ns
56
Minimum Time After Fall of SPH to 1st Read or Write
tbd
ns
58
Host Read Address Hold Time
tbd
ns
59
Host Write Data Valid
tbd
ns
60
Host Write Data Hold
tbd
ns
61
Host Read Data Enable
tbd
ns
62
Host Read Data Valid
tbd
ns
63
Host Read Data Hold
tbd
ns
64
Host Read Data Disable
tbd
ns
70
Propagation Delay for CSCCLK
tbd
ns
1. TIH and TIS are for the following input signals: PXDATA (15:0), HEN, VEN, DSYNC, STOP, EOS, BDATA
2. Assumes WINDOW signal is high.
3. Measured during clock cycle when WINDOW goes high.
4. Measured from either rise of MWE, or fall of MOE.
5. Time during which MWE = low, and MOE = high.
6. Measured from start of time when MWE = low, and MOE = High.
2.0V
INPUT
1.5V
0.45V
DEVICE
UNDER TEST
1.5V OUTPUT
A.C. testing, inputs are driven at 2.4V for a logic “1” and 0.45V for a logic “0”. Input
and output timing measurements are made a t 1.5V for both logic “1” and “0”.
Figure 1. AC TESTING INPUT, OUTPUT
From Output
Under Test
Test Point
50pF
Figure 1. NORMAL AC TEST LOAD
SYSCLK
1
2
2.0V
1.5V
0.8V
5
3
0.8V
2.0V
1.5V
4
Figure 1. System Clock Timing
23
11
RESET
Figure 1. RESET Pulse Width
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