XRT83SL28 Просмотр технического описания (PDF) - Exar Corporation
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XRT83SL28 Datasheet PDF : 47 Pages
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XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
xr
REV. 1.0.0
RECEIVER SECTION
NAME
PIN
TYPE
DESCRIPTION
RLOS7
61
RLOS6
65
RLOS5
116
RLOS4
120
RLOS3
48
RLOS2
44
RLOS1
137
RLOS0
133
O
Receive Loss of Signal
When a receive loss of signal occurs, the RLOS pin will go "High" for a mini-
mum of one RCLK cycle. RLOS will remain "High" until the loss of signal con-
dition clears. See the Receive Loss of Signal section of this datasheet for
more details.
RCLK7
58
O
Receive Clock Output
RCLK6
62
RCLK5
119
RCLK4
123
RCLK3
51
RCLK2
47
RCLK is the recovered clock from the incoming data stream. If the incoming
signal is absent, RCLK maintains its timing by using an internal master clock
as its reference. RPOS/RNEG data can be updated on either edge of RCLK
selected by RCLKinv in the appropriate global register.
NOTE: RCLKinv is a global setting that applies to all 8 channels.
RCLK1
134
RCLK0
130
RPOS7
59
RPOS6
63
RPOS5
118
RPOS4
122
RPOS3
50
RPOS2
46
RPOS1
135
RPOS0
131
O
RPOS/RDATA Output
Receive digital output pin. In dual rail mode, this pin is the receive positive
data output. In single rail mode, this pin is the receive non-return to zero (NRZ)
data output.
RNEG/LCV7
60
RNEG/LCV6
64
RNEG/LCV5
117
RNEG/LCV4
121
RNEG/LCV3
49
RNEG/LCV2
45
RNEG/LCV1
136
RNEG/LCV0
132
O
RNEG/LCV Output
In dual rail mode, this pin is the receive negative data output. In single rail
mode, this pin is a Line Code Violation indicator. If a line code violation or a bi-
polar violation occur, the LCV pin will pull "High" for a minimum of one RCLK
cycle. LCV will remain "High" until there are no more violations.
6
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