XRT83SL28 Просмотр технического описания (PDF) - Exar Corporation

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XRT83SL28

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

Exar Corporation 

xr

REV. 1.0.0

XRT83SL28

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

TABLE OF CONTENTS

GENERAL DESCRIPTION................................................................................................. 1

APPLICATIONS........................................................................................................................................... 1

FIGURE 1. HOST MODE BLOCK DIAGRAM OF THE XRT83SL28 ......................................................................................................... 1

FIGURE 2. HARDWARE MODE BLOCK DIAGRAM OF THE XRT83SL28 ................................................................................................ 2

FEATURES ..................................................................................................................................................... 3

PRODUCT ORDERING INFORMATION.................................................................................................. 3

FIGURE 3. PIN OUT OF THE XRT83SL28 ......................................................................................................................................... 4

TABLE OF CONTENTS ............................................................................................................ I

PIN DESCRIPTIONS .......................................................................................................... 5

SERIAL MICROPROCESSOR INTERFACE............................................................................................................ 5

RECEIVER SECTION ....................................................................................................................................... 6

TRANSMITTER SECTION.................................................................................................................................. 7

CONTROL FUNCTION...................................................................................................................................... 8

POWER AND GROUND (HOST AND HARDWARE MODES).................................................................................... 9

HARDWARE MODE INTERFACE ....................................................................................................................... 10

1.0 RECEIVE PATH LINE INTERFACE .................................................................................................... 14

FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH LINE TERMINATION (RTIP/RRING)................................................. 14

1.1 INTERNAL TERMINATION ............................................................................................................................ 14

TABLE 1: SELECTING THE INTERNAL IMPEDANCE ............................................................................................................................. 14

FIGURE 5. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .................................................................................... 14

1.2 PEAK DETECTOR/DATA SLICER ................................................................................................................. 15

1.3 CLOCK AND DATA RECOVERY ................................................................................................................... 15

FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK .............................................................................................. 15

FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK ............................................................................................ 15

TABLE 2: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG .......................................................................................................... 15

1.4 RECEIVE SENSITIVITY .................................................................................................................................. 16

FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY........................................................................................ 16

1.5 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ............................................................ 16

1.5.1 RLOS (RECEIVER LOSS OF SIGNAL)...................................................................................................................... 17

1.5.2 AIS (ALARM INDICATION SIGNAL) .......................................................................................................................... 17

1.5.3 LCV (LINE CODE VIOLATION DETECTION) ............................................................................................................ 17

1.6 RECEIVE JITTER ATTENUATOR .................................................................................................................. 17

1.7 HDB3 DECODER ............................................................................................................................................ 18

1.8 ARAOS (AUTOMATIC RECEIVE ALL ONES) ............................................................................................... 18

FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF THE ARAOS FUNCTION ................................................................................................ 18

1.9 RPOS/RNEG/RCLK ........................................................................................................................................ 18

FIGURE 10. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN................................................................................... 18

FIGURE 11. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN...................................................................................... 19

2.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 20

FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH................................................................................................... 20

2.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 20

FIGURE 13. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK ............................................................................................... 20

FIGURE 14. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK ................................................................................................. 20

TABLE 3: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG ........................................................................................................... 21

2.2 HDB3 ENCODER ............................................................................................................................................ 21

TABLE 4: EXAMPLES OF HDB3 ENCODING...................................................................................................................................... 21

2.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 21

TABLE 5: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS .................................................................................... 21

2.4 TAOS (TRANSMIT ALL ONES) ..................................................................................................................... 22

FIGURE 15. TAOS (TRANSMIT ALL ONES)ATAOS (AUTOMATIC TRANSMIT ALL ONES) .................................................................... 22

2.5 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ............................................................................................ 22

FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION............................................................................................... 22

2.6 TRANSMITTER POWER DOWN IN HARDWARE MODE ............................................................................. 22

2.7 DMO (DRIVER MONITOR OUTPUT) ............................................................................................................. 22

2.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 23

FIGURE 17. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ................................................................................... 23

3.0 E1 APPLICATIONS ............................................................................................................................. 24

3.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 24

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