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CXD2467Q

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD2467Q

(f) OSD signal input pins (R1OSD, R2OSD, G1OSD, G2OSD, B1OSD, B2OSD, YM1, YM2, YS1 and YS2)

These pins input OSD signals that have been demultiplexed to 1:2. The Red signal is input to R1OSD (Pins

228 and 229) and R2OSD (Pins 238 and 239), the Green signal to G1OSD (Pins 230 and 231) and G2OSD

(Pins 1 and 240), and the Blue signal to B1OSD (Pins 232 and 233) and B2OSD (Pins 2 and 3). In addition,

the YM signal is input to YM1 (Pin 236) and YM2 (Pin 4), and the YS signal to YS1 (Pin 237) and YS2 (Pin 5).

(g) Clock output pin (CLKOUT)

The internal master clock is output from CLKOUT (Pin 33).

(h) RGB signal output pins (R1OUT, R2OUT, G1OUT, G2OUT, B1OUT and B2OUT)

These pins output the arithmetically processed RGB signals in the 1:2 demultiplexed state. The Red signal is

output from R1OUT (Pins 118 to 125, 128 and 129) and R2OUT (Pins 105 to 107, 109 to 113, 116 and 117),

the Green signal from G1OUT (Pins 93 to 95, 97 to 101, 103 and 104) and G2OUT (Pins 80 to 82, 84 to 88, 91

and 92), and the Blue signal from B1OUT (Pins 68 to 71, 73 to 77 and 79) and B2OUT (Pins 56 to 65).

(i) Power saving pins (PSAVE1 and PSAVE2)

The gamma block RAM can be set to standby mode using both PSAVE1 (Pin 170) and PSAVE2 (Pin 171).

The RAM operates normally when these pins are set to low level, and enters standby mode to reduce power

consumption when set to high level. At this time data can not be set to or read from the RAM. However, data

set in advance in the RAM is held even in standby mode. In addition, the gamma block RAM output is the data

held just before the pin voltage changes to high level, so the RAM output changes according to the data set in

the RAM, etc. Therefore, using the mute function to fix the CXD2467Q output to the desired level in standby

mode is recommended.

1-2. RGB Signal and OSD Signal Pipeline Delay

The RGB signal I/O pipeline delay is 42 dot clocks. In addition, the OSD, YM and YS signal pipeline delay is 12

dot clocks. Note that the phase relationship between each clock and the RGB signals is as shown in the

figures below. This relationship is the same for the OSD, YM and YS signals.

(1) CLK1P/CLK1N and CLK1C input (CLKPOL1 = low)

HD (Active Low)

CLK1P

R1IN

R2IN

CLKOUT

R1OUT

R2OUT

N – 2 N N + 2 N + 4 N + 6 N + 8 N + 10 N+ 12 N + 14 N + 16 N + 18

N – 1 N + 1 N + 3 N + 5 N + 7 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19

N – 44 N – 42 N – 40 N – 38 N – 36 N – 34 N – 32 N – 30 N – 28 N – 26 N – 24

N – 43 N – 41 N – 39 N – 37 N – 35 N – 33 N – 31 N – 29 N – 27 N – 25 N – 23

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