CXD2467Q Просмотр технического описания (PDF) - Sony Semiconductor

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CXD2467Q

Digital Signal Driver/Timing Generator

Sony Semiconductor 

CXD2467Q

Description of Operation

1. DSD and TG Blocks

1-1. Description of Input/Output Pins

(a) Sync signal input pins (HDIN1 and VDIN1)

Horizontal and vertical separate sync signals are input to HDIN1 (Pin 22) and VDIN1 (Pin 23), respectively.

The CXD2467Q supports only non-interlace sync signals with a dot clock of 135MHz or less. Also, the HSYNC

width should be 40 dot clocks or more, and the VSYNC width, 1H or more.

(b) Sync signal polarity setting pins (HDPOL1 and VDPOL1)

The polarity of the input horizontal and vertical sync signals are set by HDPOL1 (Pin 24) and VDPOL1 (Pin

25), respectively. Set to high level for positive polarity, and to low level for negative polarity.

(c) Master clock input pins (CLK1P/CLK1N, CLK1C and CLK2) and clock selection pins (CLKSEL1 and CLKSEL2)

Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The

1/N (N is the number of clocks during one horizontal period) frequency-divided dot clock pulse is output from

HRET (Pin 51) for the external phase comparator.

The master clock input pins consist of CLK1P/CLK1N (Pins 26 and 27) for small-amplitude differential input

(center level: 2.0V, amplitude: ±0.4V), and CLK1C (Pin 29) and CLK2 (Pin 31) for CMOS level input for a total

of three channels. These are selected according to CLKSEL1 (Pin 35) and CLKSEL2 (Pin 36).

CLKSEL1

L

H

—

CLKSEL2

L

L

H

Selected clock input pins

CLK1P/CLK1N (small-amplitude differential input, input at the same frequency as

the dot clock)

CLK1C (CMOS level input, input at the same frequency as the dot clock)

CLK2 (CMOS level input, input at 1/2 the frequency of the dot clock)

—: Don't care

(d) Clock polarity switching pin (CLKPOL1)

When CLK1P/1N or CLK1C is selected, the clock is 1/2 frequency divided inside the IC using the falling edge

of the HD pulse as the reference. The polarity of this 1/2 frequency-divided clock is switched by CLKPOL1 (Pin

37). Normally CLKPOL1 is used at low level.

CLK1P

HDIN1 (Active Low)

Internal clock for

DSD and TG blocks

CLKPOL1 = L

CLKPOL1 = H

(e) RGB signal input pins (R1IN, R2IN, G1IN, G2IN, B1IN and B2IN)

These pins input RGB signals that have been demultiplexed to 1:2. The Red signal is input to R1IN (Pins 172,

173 and 176 to 181) and R2IN (Pins 182 to 185 and 188 to 191), the Green signal to G1IN (Pins 192 to 197,

199 and 200) and G2IN (Pins 201 to 208), and the Blue signal to B1IN (Pins 211 to 218) and B2IN (Pins 219 to

221 and 223 to 227).

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