W48S87-04(1999) Просмотр технического описания (PDF) - Cypress Semiconductor
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W48S87-04 Datasheet PDF : 21 Pages
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PRELIMINARY
W48S87-04
Writing Data Bytes
Each bit in the data bytes control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 0–6. Table 5 details additional frequency selections that
are available through the serial data interface. Table 6 details
the select functions for Byte 0, bits 1 and 0.
Table 4. Data Bytes 0–6 Serial Configuration Map
Affected Pin
Bit Control
Bit(s) Pin No. Pin Name
Control Function
0
1
Data Byte 0
7
--
--
(Reserved)
--
--
6
--
--
BYT0_SEL2
Refer to Table 5
5
--
--
BYT0_SEL1
Refer to Table 5
4
--
--
BYT0_SEL0
Refer to Table 5
3
BYT0 _FS#
Frequency
Frequency
Controlled by
Controlled by
FS (2:0)
BYT0_SEL (2:0)
2
22
(Reserved)
1–0
--
--
Bit 1 Bit 0
Function (See Table 6 for function details)
0
0
Normal Operation
0
1
Test Mode
1
0
Spread Spectrum On
1
1
All Outputs Three-stated
Data Byte 1
7
26
48MHZ Clock Output Disable
Low
Active
6
25
24MHZ Clock Output Disable
Low
Active
5
--
--
(Reserved)
--
--
4
--
--
(Reserved)
--
--
3
40
CPU3 Clock Output Disable
Low
Active
2
41
CPU2 Clock Output Disable
Low
Active
1
43
CPU1 Clock Output Disable
Low
Active
0
44
CPU0 Clock Output Disable
Low
Active
Data Byte 2
7
--
--
(Reserved)
--
--
6
7
PCI_F Clock Output Disable
Low
Active
5
15
PCI5
Clock Output Disable
Low
Active
4
13
PCI4
Clock Output Disable
Low
Active
3
12
PCI3
Clock Output Disable
Low
Active
2
11
PCI2
Clock Output Disable
Low
Active
1
10
PCI1
Clock Output Disable
Low
Active
0
8
PCI0
Clock Output Disable
Low
Active
Default
0
0
0
0
0
0
00
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
8
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